Hi ,
I want to simulate arm inorder multicore system , first i want to collect
trace with simple memory and use trace cpu to simulate my own memory system
I tried following tutorial but the trace i am able to get for 03 cpu only,
timing simple cpu is not supported
While running its giving error A
I understand; thanks again for the details.
On Wed, Jul 5, 2023 at 7:10 PM Matt Sinclair
wrote:
> Answers:
>
> 1. Yes, I believe so. However, I have never personally tried using the
> O3 model with the GPU. Matt P has, I believe, so he may have better
> feedback there.
>
> 2. I have not foll
Greetings,
If I want to, for example, add a delay of 100 ticks before a line of code
executes in the function handleTimingReqMiss() in cache.cc, how do I go
about doing that?
--
Regards,
John Smith
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To u
I've looked into the schedule() function which is used to schedule events.
But can this function be used to simulate delays?
On Thu, Jul 6, 2023 at 11:12 AM John Smith
wrote:
> Greetings,
> If I want to, for example, add a delay of 100 ticks before a line of code
> executes in the function handl
On 7/6/2023 11:12 AM, John Smith via gem5-users wrote:
Greetings,
If I want to, for example, add a delay of 100 ticks before a line of code executes in the function
handleTimingReqMiss() in cache.cc, how do I go about doing that?
Generally speaking, you'll have to schedule an event and then do
On 7/6/2023 12:48 PM, John Smith via gem5-users wrote:
I've looked into the schedule() function which is used to schedule events. But can this function be
used to simulate delays?
Not by itself. You schedule an event at something like curTick() + 100.
When the event happens, a function gets ca
Hi John,
The following may be helpful:
https://gem5bootcamp.github.io/gem5-bootcamp-env/modules/developing%20gem5%20models/events/
https://www.youtube.com/watch?v=OcXA1D4b1RA&t=3868s
Cheers,
Jason
On Thu, Jul 6, 2023 at 9:53 AM Eliot Moss via gem5-users <
gem5-users@gem5.org> wrote:
> On 7/6/2
In my configuration I used CPUTypes.O3 and PrivateL1SharedL2CacheHeirarchy
to check how clflush and fence impacts the timing of workload. In my
workload I run 10,000 iteration to update an array value, 200 updates per
thread. In workload, I have :
for( ;index ARR[index]=thread_ID;
> FLUSH(&ARR[ind
Okay, I understood. Thanks.
On Thu, Jul 6, 2023 at 12:57 PM Jason Lowe-Power
wrote:
> Hi John,
>
> The following may be helpful:
>
>
> https://gem5bootcamp.github.io/gem5-bootcamp-env/modules/developing%20gem5%20models/events/
> https://www.youtube.com/watch?v=OcXA1D4b1RA&t=3868s
>
> Cheers,
> J
Hi,
I am trying to set accurate latency numbers for my test system, and I noticed a
weird thing happening in the logs.
My system.clk_domain.clock is 1000 so that should mean 1000 ticks equal to 1
cycle. I noticed that the time it takes for LD to finish is
(4761575500−4761566500) which is 9000
Hi everyone,
I have a doubt regarding the operation of the recvAtomic() function in the
memory controller. I can see that recvAtomic() calls recvAtomicLogic(),
which returns the access latency from the memory interface. If I change the
code to:
return mem_intr->accessLatency() + 100;
Does this mea
Hi John,
What's the exact stat you are looking at for AMAT? My guess is that it is
not getting updated for Atomic mode memory accesses.
interface. If I change the code to:
> return mem_intr->accessLatency() + 100;
> Does this mean that it will take 100 more ticks for the memory controller
> to ac
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