Hi, I am trying to set accurate latency numbers for my test system, and I noticed a weird thing happening in the logs.
My system.clk_domain.clock is 1000 so that should mean 1000 ticks equal to 1 cycle. I noticed that the time it takes for LD to finish is (4761575500−4761566500) which is 9000 ticks i.e. 9 cycles, but the debug print says that it took 18 cycles. Am I missing something here? It would be great if someone could clarify on this. [image] Thanks and Regards, Gautam
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