Thanks, I'll check it out.
Best Regards,
*Eng. Karim Soliman*
Teaching Assistant
Computer Engineering Department
Pharos University in Alexandria (P.U.A)
On Fri, Mar 3, 2023 at 9:35 PM Krishna, Tushar
wrote:
> Take a look at outportComputeXY for some reference ..
>
> Cheers,
> Tushar
>
> On Mar
Hi,
Sorry to disturb you. When I run the DNNMark test_bwd_bn, I found the
error.
```
sh: 1: Cannot fork
MIOpen(HIP): Error [ValidateGcnAssemblerImpl] Specified assembler does not
support AMDGPU. Expect performance degradation.
```
I saw other people who had the same problem, but it doesn't s
Can you please provide more information about what the problem is? The
error message you posted is lacking context. Specifically what input size
were you trying to use? And did you generate the appropriate cachefiles
before running, as mentioned here:
http://resources.gem5.org/resources/dnn-mark?
Hi all,
What is the 'IprAccess' op_class in Gem5? I have seen it in the
O3_ARM_v7a.py and other O3 CPU configurations, and I can't find any comment
or relevant information on Google.
Thanks
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Hi,
IPR is Interrupt Priority Register in ARM.
I looked it up,
But Instructions used to access the IPR can vary depending on the specific
implementation of the processor and the Interrupt Controller being used.
So, I think that why the Instructions classified as ‘IprAccess’ is not
implement
Hi Haseung,
Got it, thanks for your reply.
Maybe we can add some new opClass for the different implementation.
Cheers,
Zhong
봉하승 via gem5-users 于2023年3月6日周一 11:53写道：
> Hi,
>
> IPR is Interrupt Priority Register in ARM.
>
> I looked it up,
>
> But Instructions used to access the IPR can vary
Hi Ayaz,
do you know any examples or specific parts of the source code that I should
look at? Do you have any hints or tips how I can implement my use case?
Thank you in advance,
Sebastian
Von: Sebastian Weber via gem5-users
Gesendet: Montag, 20. Februar 2023 11:27
An: Ayaz Akram
