[gem5-users] Dumping stats periodically based on number of instructions for multi-CPU system

2023-01-26 Thread Prakhar Diwan via gem5-users
Hello, I am running multi-programmed workloads in SE mode. I want to dump statistics after cpu[i] has completed num_instrs_cpu[i] instructions [for all i in range(num_cpus)] i.e. I want to schedule events: after cpu[0] completes num_instrs_cpu[0] instructions, after cpu[1] completes num_instrs_cpu

[gem5-users] RV32 SIMULATION with gem5

2023-01-26 Thread Ayan Ray via gem5-users
Hi , I want to simulate risc-32 with gem5. I am able to find resources for RV64 , anyway guidelines or steps for RV32 ? Thanks ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org

[gem5-users] Re: RV32 SIMULATION with gem5

2023-01-26 Thread Juan García Blanco via gem5-users
Hi, AFAIK, there are relevant changes to RV32 in the develop branch. You might want to try using that branch. Regards, Juan ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org

[gem5-users] Re: RV32 SIMULATION with gem5

2023-01-26 Thread Ayan Ray via gem5-users
HI Juan/all, I am comparatively new to simulating with RISC ISA, can anybody point me to the steps for setup ? Thanks On Thu, Jan 26, 2023 at 5:01 PM Juan García Blanco wrote: > Hi, > > AFAIK, there are relevant changes to RV32 in the develop branch. You > might want to try using that branch.

[gem5-users] Re: RV32 SIMULATION with gem5

2023-01-26 Thread RTL Insn via gem5-users
Hi, Build the Gem5 for ARM architecture. On Thu, Jan 26, 2023 at 3:06 PM Ayan Ray via gem5-users wrote: > HI Juan/all, > > I am comparatively new to simulating with RISC ISA, can anybody point me > to the steps for setup ? > Thanks > > On Thu, Jan 26, 2023 at 5:01 PM Juan García Blanco > wrote:

[gem5-users] Re: RV32 SIMULATION with gem5

2023-01-26 Thread Juan García Blanco via gem5-users
Hi, I think you should go through the 'Getting Started' guide on the web, it's very well written and it's updated. That will give you an idea of how to set up a RISCV or other RISC simulator. And, as I said, the develop branch of the repo contains changes to the RV32 implementation. Thus, if yo

[gem5-users] RISCV fs mode - code won't stop running

2023-01-26 Thread Priyanka Ankolekar via gem5-users
Hello, I am new to gem5. I am trying to run Dhrystone on gem5 RISCV using the fs_linux.py file in the gem5 repo. configs/example/riscv/fs_linux.py Here is the command I am using: ./build/RISCV/gem5.opt --debug-start=0 --debug-flags=Exec --debug-file=trace.out ./configs/example/riscv/fs_linux.py

[gem5-users] cache line data based on memory accesses

2023-01-26 Thread Ghadeer Almusaddar via gem5-users
Hello All, Is there any direct way in gem5 by which I can get the data of the whole cache line for every memory read or write regardless of how many bytes are read or written from that cache line? I also want to dump cache line data due to memory accesses from a specific core (requestorId)? Thank