Hi all,
I came to the point where I'll have to add some new instructions to gem5.
Something like load a number of bytes and process.
I have some "high-level" questions that I'd like to ask for more experienced
users, so that I don't find myself in a dead-end later on.
1 - First, pseudo-instruc
Just to partially answer my own question 2.
I just realized that M5 ops are pseudo instructions and they work with KVM
("_addr" version), so I guess I could manage to do the same with my own
instructions, if I was to implement them as pseudo-instructions.
I still don't know if there is a way to
Hi Pedro,
As you correctly stated, you could make an instruction work in KVM mode by
implementing them as pseudo instruction and using the memory mapped
implementation (m5 –addr).
If you run your instruction in KVM mode, the host won’t recognize the
instruction and your guest VM will get an Un
Hi Giacomo,
First of all, thanks for your time answering the question.
Your assumption about KVM is correct. I just use it to fast-forward, and I do
not need to execute the instruction I want to implement in KVM mode.
Long story short: the same code for the ROI is executed during the
fast-forw
I suggest you have a look at how memory mapped m5ops are implemented:
https://github.com/gem5/gem5/blob/develop/src/arch/arm/mmu.cc#L185
If the memory reference lies within a specific address range (m5opRange) the
memory access is replaced by the local accessor callback (recorded in the
Request
Thank you for the detailed answer, Giacomo.
I think case (2) will cover what I want to do. (1) is ok, but since my
instruction will load data from memory, the number of cycles will depend on
where the source data is in the memory hierarchy and I'm not sure I'll be able
to model all involved cos
Hi,
We are working on implementing a replacement policy in the gem5. This
policy actually keeps track (i.e., history) of the memory references from
the LD/ST instructions in order to train the predictor. Also, it predicts
which cache blocks to evict and what other blocks from later memory levels
t
Hi,
Gabriel
I'm not interested in a specific gem5 component. I have a microbenchmark
that makes use of the srand and rand functions with srand() being seeded by
using time.
struct timeval t1;
gettimeofday(&t1, NULL);
srand(t1.tv_usec * t1.tv_sec);
I assume that gem5 always uses the same time for
Hi All,
I am exploring and testing out a few modifications to the MESI cache
coherence protocol. I am dropping out a load/store, i.e., GETX /GETS
request at the directory controller if the block is in a transient state.
My goal is to reissue these loads and stores from the L1 cache controller
agai
