[gem5-users] Re: Vector Instructions Support

Hi Thanks for the information. I will check the code base for that. Do you have any suggestions for the documentation regarding it ? Regards Nitesh On Thu, 28 Oct 2021 at 17:53, Jason Lowe-Power wrote: > Hello, > > For Arm, gem5 has SVE support and (some/most/all?) of the NEON > instructions.

[gem5-users] Problem POWER ISA restore checkpoints generated by SimPoint

Hello, I recently used gem5 to start POWER ISA research. I meet a problem with restoring checkpoint on SE mode. I tried to use SimPoint to generate some checkpoints in one of the SPEC2017 test cases and want to restore the checkpoints. Here are my steps: (1)Using the Valgrind to generate BBV f

[gem5-users] Re: Vector Instructions Support

Hi Nitesh, I don't think there's any good documentation. This may help with Arm SVE support, but it's from a while ago. Things have changed since 2018. https://community.arm.com/arm-research/b/articles/posts/simulating-the-arm-sve-with-gem5 On Fri, Oct 29, 2021 at 2:27 AM Nitesh Narayana GS wrot

[gem5-users] Re: Vector Instructions Support

Thanks Jason This is a great start and help for me! On Fri, 29 Oct 2021 at 16:43, Jason Lowe-Power wrote: > Hi Nitesh, > > I don't think there's any good documentation. This may help with Arm SVE > support, but it's from a while ago. Things have changed since 2018. > https://community.arm.com/a

[gem5-users] GPU virtual memory system

Hello, I have been looking at the source code of the GPU model for the past few weeks, and I had some doubts about the virtual memory system for discrete GPUs (and APUs if there are any differences). I will include my questions and partial answers below, and I hope you can correct me if I'm wron

[gem5-users] 答复: Re: How to enable KVM unitest on ARM server

If I build gem5.opt of ARM on X86 server, the print “Info: KVM for null not supported on arm host.” will also be presented 发件人: Gabe Black via gem5-users [mailto:gem5-users@gem5.org] 发送时间: 2021年10月29日 11:43 收件人: gem5 users mailing list 抄送: Gabe Black 主题: [gem5-users] Re: How to enable KVM unite

[gem5-users] How to specify the operation time setting of a custom instruction

Hi all, I've added custom instructions to the RISC-V ISA by modifying the contents of/src/arch/riscv/ISA/decoder and it works properly. But I want to know how to specify the operation time setting of a custom instruction, such as specifying which functional unit it executes in and how many cycl

[gem5-users] Re: Instruction execute stage clock cycles in MinorCPU

Hi Volkan, I've noticed that you've been working on RISC-V in gem5 and I'd like to ask you some questions. I've added custom instructions to the RISC-V ISA by modifying the contents of/src/arch/riscv/ISA/decoder and it works properly. But I want to know how to specify the operation time settin

[gem5-users] Re: How to enable KVM unitest on ARM server

I found it in the revision history. If you're building the "NULL" target, you should not set USE_KVM to true. If you do, then it will try to verify that the simulated architecture and the host architecture is the same, which is the only time KVM will work. This "Info" print out is just telling you

[gem5-users] 答复: Re: How to enable KVM unitest on ARM server

That’s exactly what you said. Another problem in system test, if I follow the gem5 system test, there are some failed case like this: Logging call to command: ./build/ARM/gem5.opt -d /tmp/gem5outes8xx6ry -re /home/l00515693/KSim_LightESL/tests/gem5/cpu_tests/run.py --cpu=AtomicSimpleCPU ./test