Hi Thanks for the information. I will check the code base for that. Do you have any suggestions for the documentation regarding it ?
Regards Nitesh On Thu, 28 Oct 2021 at 17:53, Jason Lowe-Power <ja...@lowepower.com> wrote: > Hello, > > For Arm, gem5 has SVE support and (some/most/all?) of the NEON > instructions. For x86, we support most 128-bit SIMD instructions, but very > few or no 256-bit or 512-bit SIMD instructions. I have heard of > forks/groups that have implemented many of the x86 vector instructions, and > I have heard that RISC-V vector extensions have been implemented. However, > these implementations have not been made public or have not been pushed > upstream. > > Cheers, > Jason > > On Thu, Oct 28, 2021 at 4:08 AM nitesh--- via gem5-users < > gem5-users@gem5.org> wrote: > >> Hi >> >> I am working on understanding VPUs and vector instructions, and am a bit >> new to the gem5 environment. I aI wanted to know if there is any official >> update on the vector instruction support for gem5 x86 and ARM? I see there >> are some forked versions available in the community but I am skeptical >> about their stability and version. Would like to know if anyone recommends >> any such version. >> >> I also see In this link >> https://www.gem5.org/documentation/general_docs/architecture_support/ >> that gem5 has support for SSE in x86 but see little documentation regarding >> that. Also no mention of ARM vector instruction support. >> >> Sorry if I am wrong regarding the things I have mentioned. >> >> So any guidance, help, or advice regarding this will be great!! >> >> Thanks >> _______________________________________________ >> gem5-users mailing list -- gem5-users@gem5.org >> To unsubscribe send an email to gem5-users-le...@gem5.org >> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s >> >
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