[gem5-users] Re: Support for CAS (compare and swap) instruction in ARM arch

Thanks a lot Giacomo. By default (without ruby), I am able to run my microbenchmark now; but I am trying to use the ruby side for memory modelling- I need to model CAS using that and also be able to use ARM HTM feature but when I run using "--ruby", I get the following panic message: *"build/ARM_ME

[gem5-users] set cache line size under o3 cpu

When I simulate o3 cpu, I find that I can not set cache line size to 32B. The command is ./build/RISCV/gem5.opt --outdir=output/riscv configs/example/se.py \ --cpu-type=DerivO3CPU --num-cpus=2 --cpu-clock=1.5GHz --caches --l2cache --l1d_size=16kB \ --l1i_size=16kB --l2_size=256kB --l1d_assoc=4 -

[gem5-users] encounter a problem when using O3 CPU under PowerPC ISA

When I use the following command to simulate, I encounter a problem. ./build/POWER/gem5.opt --outdir=output/powerpc configs/example/se.py \ --cpu-type=DerivO3CPU --num-cpus=1 --cpu-clock=132MHz --caches --l2cache --l1d_size=32kB \ --l1i_size=32kB --l2_size=1MB --l1d_assoc=8 --l1i_assoc=8 --l2_asso

[gem5-users] Re: set cache line size under o3 cpu

Hello This is because the fetchBufferSize in O3CPU.py is set to 64 bytes and you are trying to set the cache line size to 32 bytes. In your local version of se.py, add the following code: if (options.cacheline_size == 32): DerivO3CPU.fetchBufferSize = 32 Best regards J.Osmany -Origin