[gem5-users] Re: Stores always cause SC_Failed in Ruby/SLICC protocol

Hi Theo, There are a number of poorly documented "rules" to writing SLICC protocols. One rule is that you should not do *anything* other than trigger a transition (call trigger()) in a in_port. This sounds like the underlying problem that you ran into. Another rule that isn't documented is that t

[gem5-users] Re: RISC-V Full System Simulation

Hi Ali, See https://gem5.googlesource.com/public/gem5/+/refs/heads/master/RELEASE-NOTES.md#new-features. In gem5-20, we added *some* support for full system RISC-V, but not quite enough to boot Linux. TBH, I'm not sure exactly what support is missing. Nils might be able to answer better than I can

[gem5-users] Re: RISC-V Full System Simulation

Hi Jason, Thanks for your reply. This is good news! Actually, I want to see the impact of TLB misses in my simulations, which SE mode of gem5 is not suitable. I will wait for Nils to see if TLB investigations are possible in gem5-20, and if it's not what is left and where I can look. Thanks, Ali

[gem5-users] Re: RISC-V Full System Simulation

Hi Ali, The TLB and page table walker (PTW) have been implemented for RISC-V (sv39 paging). However, since Linux doesn't boot, unless you're running your program bare metal, I'm not sure if this support will be helpful. Cheers, Jason On Mon, Jul 6, 2020 at 9:14 AM Ali Hajiabadi wrote: > Hi Jas

[gem5-users] Re: Syntax Error in gem5 while using bitset template.

Hi Vipin, I don't think you can use templated types in SLICC (in all cases). There have been a few hacks over the years for special cases (if I'm remembering correctly). That said, the easiest thing to do would be to use something other than a bitset in your object. You should be able to use Mach

[gem5-users] gem5-20.1 roadmap

Hi all, We have just posted the gem5-20.1 roadmap to the gem5 website: http://www.gem5.org/project/2020/07/01/gem5-20-1-roadmap.html After our successful release of gem5-20, it’s