Hi Ali,

The TLB and page table walker (PTW) have been implemented for RISC-V (sv39
paging). However, since Linux doesn't boot, unless you're running your
program bare metal, I'm not sure if this support will be helpful.

Cheers,
Jason

On Mon, Jul 6, 2020 at 9:14 AM Ali Hajiabadi <ahajiabad...@gmail.com> wrote:

> Hi Jason,
>
> Thanks for your reply. This is good news!
>
> Actually, I want to see the impact of TLB misses in my simulations, which
> SE mode of gem5 is not suitable. I will wait for Nils to see if TLB
> investigations are possible in gem5-20, and if it's not what is left and
> where I can look.
>
> Thanks,
> Ali
>
> On Mon, Jul 6, 2020 at 8:26 PM Jason Lowe-Power <ja...@lowepower.com>
> wrote:
>
>> Hi Ali,
>>
>> See
>> https://gem5.googlesource.com/public/gem5/+/refs/heads/master/RELEASE-NOTES.md#new-features.
>> In gem5-20, we added *some* support for full system RISC-V, but not quite
>> enough to boot Linux. TBH, I'm not sure exactly what support is missing.
>> Nils might be able to answer better than I can.
>>
>> Cheers,
>> Jason
>>
>> On Sun, Jul 5, 2020 at 2:10 AM Ali Hajiabadi via gem5-users <
>> gem5-users@gem5.org> wrote:
>>
>>> Hi everyone,
>>>
>>> I have been recently interested in performing full-system simulation for
>>> RISC-V. Is this possible with the current version of gem5? I found this
>>> thesis that tries to enable full-system simulation [1] but it's a little
>>> bit old and they do not provide an open source implementation. Is this
>>> enabled in the current version of gem5? If it's not, can you give me some
>>> leads on how to enable it?
>>>
>>> Thanks,
>>> Ali
>>>
>>> [1]
>>> https://cfaed.tu-dresden.de/files/Images/people/chair-cc/theses/1808_Scheffel.pdf
>>>
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>>
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