Is it so ?
On Fri, Oct 30, 2015 at 7:13 PM, P Pinky wrote:
> Hi all
> Why do we have tablewalker cache ?
>
> From the description " X86: *Add* *L1* *caches* for the *TLB* *walkers*.
> Small *L1* *caches* are connected to the *TLB* *walkers* when *caches *are
> used. This allows them to participa
Hello,
I assume that back-end pipe widths (issue, wb, commit and squash) are the
same. For a 2-way processor, an issue-width of 4 can be fine.
Regards,
--
Fernando A. Endo, Post-doc
INRIA Rennes-Bretagne Atlantique
France
2015-08-28 1:56 GMT+02:00 Rizwana Begum :
> Hello All,
>
> I am trying
Hello,
It seems to be a compilation related issue. If pthread.o is replaced by
-lpthread it may work. Note that pthread.o may be a gem5 modified threading
library.
Regards,
--
Fernando A. Endo, Post-doc
INRIA Rennes-Bretagne Atlantique
France
2015-09-02 9:56 GMT+02:00 Azadeh Shirvanian :
> H
Hello,
1. arm_detailed can be used to run aarch64
2. the config file is configs/common/O3_ARM_v7a.py
Regards,
--
Fernando A. Endo, Post-doc
INRIA Rennes-Bretagne Atlantique
France
2015-09-02 11:05 GMT+02:00 Virendra Kumar Pathak
:
> Hi gem5 group,
>
> I am new to gem5 and working on adding
Hello,
You can use the gem5 instruction rpns() (from util/m5/m5op.h) in your code,
as if it was a gettime or cycle counter. It gives the nanosecs elapsed
since the begining.
Regards,
--
Fernando A. Endo, Post-doc
INRIA Rennes-Bretagne Atlantique
France
2015-09-04 22:59 GMT+02:00 Marcos Horro
Hello,
LPAE seems to be a Kernel feature, hence you may need to recompile your
Linux Kernel with the right flag config. You can also look for precompiled
kernels in ARM Linux communities (linaro, Ubuntu, Debian).
Regards,
--
Fernando A. Endo, Post-doc
INRIA Rennes-Bretagne Atlantique
France
2
Could you develop a bit more your question?
--
Fernando A. Endo, Post-doc
INRIA Rennes-Bretagne Atlantique
France
2015-09-27 13:48 GMT+02:00 f.nakhaee :
> I want to determine the output quality if critical path violation occurred
> in the presence of aging. For this reason I want to know if it
Hello,
Regarding [1], the instruction latencies of a A15 can be set as those of
the A9 in [2], or as those of an A72 (
http://infocenter.arm.com/help/topic/com.arm.doc.uan0016a/cortex_a72_software_optimization_guide_external.pdf
)
Best regards,
--
Fernando A. Endo, Post-doc
INRIA Rennes-Bretagn
Hi,
I have similar doubt regarding extending the number of pipeline stages in
gem5.
I am trying to extend default 7-stage o3 cpu pipeline to 15-stage.
Any guidance on below questions will be highly appreciated.
1) How the delay parameters like decodeToFetchDelay & fetchToDecodeDelay
are used in
Hi all,
In the FS mode, I connect to the simulated OS with m5term. Then in the
terminal, I first set up the localhost with the following commands:
# ifconfig lo 127.0.0.1
# route add -net 127.0.0.0 netmask 255.0.0.0 lo
Then I can ping the localhost successfully. But when I try to ssh
localhost, I
Hello Pierre/Fernando,
Thanks for your replies.
Based on [1] the ROB entries for cortex-A15 is 60. However, as per this
article
http://www.anandtech.com/show/6787/nvidia-tegra-4-architecture-deep-dive-plus-tegra-4i-phoenix-hands-on/2,
the
number of ROB entries are 128. I did run some tests changi
Hi,
1) fetchToDecodeDelay is used by Decode to pick instructions that were fetched
fetchToDecodeDelay cycles ago, so really, it increases the pipe latency.
Same for the others, although if you increase issueToExecute delay beyond 1, I
believe that you will forbid two instructions to execute ba
Hi
I am Bhaskar. I am a final year B.E student. For my final year project I am
using the gem5 simulator. I need to collect the stack distance of programs
using gem5. I used the --debug-flag="StackDist", but it did not print
anything. I also tried setting the verifyStack flag in
mem/stack_dist_calc.
Hi all
I am trying to implement an existing paper which uses TLB to
store the private/shared data information . How the Coherence protocols
communicate with TLB inorder to store the private/sharer information as one
of the fields in TLB entry.? Can someone give any ideas for this ?
T
14 matches
Mail list logo