To avoid confusion, I merely wanted to highlight that there is a
difference between ARMv7 and ARM Cortex-A7. The former is an ISA, the
latter an in-order (and not out-of-order) core.
Andreas
On 17/10/2014 01:33, "Naveed Ul Mustafa via gem5-users"
wrote:
>
>Thanks for reply
>
>I applied ur sugge
Hello
I need to profile all accesses to physical memory(DRAM) including address
and data.
I did scons for ARM architecture in SE mode; is there any clue where & how
I should add my listeners?
Best Regards
Farshid Hajhashemi
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gem5-users mailing list
ge
Hi all
I'm trying to create a heterogeneous system with 1 2-way 2 4-way and 1
8-way core in arm-detailed FS mode.
Following is the change I made in fs.py:
cpus = []
for i in xrange(4):
if(i == 0):
cpus.append(2-way)
elif (i == 1):
cpus.append(4-way)
elif (i ==
I am collecting some histogram data that is getting printed out to
stats.txt. The problem I am having is that the buckets are getting printed
out in scientific notation. I have been looking around in the code and
documentation and it isn't immediately obvious to me how to change that.
Does anyo
Patrick L. via gem5-users gem5.org> writes:
>
> I am collecting some histogram data that is getting printed out to
> stats.txt. The problem I am having is that the buckets are getting
printed
> out in scientific notation. I have been looking around in the code and
> documentation and it isn'
Hi Andreas,
can you please provide some hint to solve the problem? am I making a
mistake when I cross compile the source code of dijkstra for Cortex- A7.
Any help will be musch appreciated.
> To avoid confusion, I merely wanted to highlight that there is a
> difference between ARMv7 and ARM Cor
Hi Prateek,
I'm trying to do something very similar to what you were. Would you please
let me know what was the if-else ladder problem that you were mentioning?
I'm a bit stuck at this point and would appreciate any help on this.
Thanks,
Poovaiah
On Wed, Apr 9, 2014 at 12:25 PM, Prateek Gupta w
