To avoid confusion, I merely wanted to highlight that there is a
difference between ARMv7 and ARM Cortex-A7. The former is an ISA, the
latter an in-order (and not out-of-order) core.
Andreas
On 17/10/2014 01:33, "Naveed Ul Mustafa via gem5-users"
<gem5-users@gem5.org> wrote:
>
>Thanks for reply
>
>I applied ur suggested option as shown below
>
>root.system.cpu.workload=LiveProcess(cmd= 'Mibench/input.dat >
>Mibench/output_small.dat', executable ='Mibench/dijkstra_small_obj')
>
>but still I get same error.
>
>
>> Dijkstra from MiBench takes an argument, have you passed it when
>>invoking
>> gem5? It should be -o input.dat
>> Em 17/10/2014 00:56, "Naveed Ul Mustafa via gem5-users"
>> <gem5-users@gem5.org>
>> escreveu:
>>
>>> Hi all,
>>>
>>> I am trying to run the dijkstra benchmark from Mibench mark suit on
>>> Cortex
>>> A7 processor. Follwing is the script for my system.
>>> --------------------------------------------
>>> import optparse
>>> import sys
>>> import m5
>>> from m5.defines import buildEnv
>>> from m5.objects import *
>>> from m5.util import addToPath, fatal
>>> addToPath('../common')
>>> from FSConfig import *
>>> from SysPaths import *
>>> from Benchmarks import *
>>> import Simulation
>>> import CacheConfig
>>> import MemConfig
>>> from Caches import *
>>> import Options
>>> from O3_ARM_v7a import *
>>>
>>>
>>> parser = optparse.OptionParser()
>>> parser.add_option("--num_cpus", type="int")#adding a new option for
>>> script
>>> parser.add_option("--clock1",type= "string")
>>> parser.add_option("--voltage1",type="string")
>>> parser.add_option("--I_Cache",type="string")
>>> parser.add_option("--D_Cache",type="string")
>>> parser.add_option("--TLB_Size",type="string")
>>> Options.addCommonOptions(parser)
>>> Options.addFSOptions(parser)
>>> (options, args) = parser.parse_args()
>>>
>>> #define one O3ARM7 core with 2GHz clock, 1mV operational voltage, and
>>> 32MB
>>> level1 Instruction and Data cache
>>> #first define a clock and voltage domain
>>> VoltageDomain1=VoltageDomain(voltage = options.sys_voltage)
>>>
>>> ClkVltDomain1=SrcClockDomain(clock=options.clock1,voltage_domain =
>>> VoltageDomain1)
>>> #define O3ARM7core
>>> core1=O3_ARM_v7a_3()
>>> #assign id to core
>>> core1.cpu_id=0
>>> #bind this core with clock and voltage domain define above
>>> core1.ClockDomain=ClkVltDomain1
>>> #define cache L1 Instruction Cache
>>> L1ICache=O3_ARM_v7a_ICache(size=options.I_Cache)
>>> #define cache L1 Data Cache
>>> L1DCache=O3_ARM_v7a_DCache(size=options.D_Cache)
>>>
>>>
>>> #define L2 TLB
>>> ArmTLB=O3_ARM_v7aWalkCache()
>>> ArmTLB.size=options.TLB_Size
>>>
>>> #Add L1 caches and L2 TLB to the core
>>> core1.addTwoLevelCacheHierarchy(L1ICache,L1DCache,ArmTLB)
>>>
>>> #Craete the system with simple memory
>>> mysystem = System(
>>> cpu=core1,
>>> physmem = SimpleMemory(),
>>> membus = CoherentXBar(),
>>> mem_mode = 'timing'
>>> )
>>>
>>> #connect slave port of membus with system port
>>> mysystem.system_port=mysystem.membus.slave
>>> #connect master port of membus with port of physical memory
>>> mysystem.physmem.port=mysystem.membus.master
>>>
>>> # create the interrupt controller
>>> core1.createInterruptController()
>>> core1.connectAllPorts(mysystem.membus)
>>>
>>> # Create a top-level voltage domain
>>> mysystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
>>> # Create a source clock for the system and set the clock period
>>> mysystem.clk_domain = SrcClockDomain(clock =
>>> options.sys_clock,voltage_domain = mysystem.voltage_domain)
>>>
>>>
>>> #declare the root
>>> root = Root(full_system=False,system = mysystem)
>>>
>>> #assign the work load to the system, read data from input.dat and write
>>> output to output_small.dat
>>>
>>> root.system.cpu.workload=LiveProcess(cmd= 'Mibench/input.dat >
>>> Mibench/output_small.dat', executable ='Mibench/dijkstra_small_obj')
>>>
>>>
>>>
>>> # instantiate configuration
>>> m5.instantiate()
>>>
>>> exit_event = m5.simulate()
>>> print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
>>> --------------------------------------------
>>>
>>> I first cross compiled the source code of dijkstra bench mark on my
>>> linux
>>> for arm using following command.
>>>
>>> arm-linux-gnueabi-gcc -static dijkstra_small.c -o dijkstra_small_obj
>>>
>>> then specified that executeable binary as workload to the system, as
>>> specified in the script above.
>>>
>>> However, when I build the above script using following command
>>>
>>> build/ARM/gem5.opt configs/MyScripts/Stage0_P1.py --num_cpus=1
>>> --clock1=1000MHz --I_Cache=32kB --D_Cache=32kB --TLB_Size=512kB
>>>
>>> I get following error
>>>
>>> gem5 Simulator System. http://gem5.org
>>> gem5 is copyrighted software; use the --copyright option for details.
>>>
>>> gem5 compiled Oct 1 2014 19:17:30
>>> gem5 started Oct 17 2014 01:53:58
>>> gem5 executing on naveed-desktop
>>> command line: build/ARM/gem5.opt configs/MyScripts/Stage0_P1.py
>>> --num_cpus=1 --clock1=1000MHz --I_Cache=32kB --D_Cache=32kB
>>> --TLB_Size=512kB
>>> Global frequency set at 1000000000000 ticks per second
>>> 0: system.cpu.isa: ISA system set to: 0 0xbe30200
>>> 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
>>> info: Entering event queue @ 0. Starting simulation...
>>> info: Increasing stack size by one page.
>>> Usage: dijkstra <filename>
>>> Only supports matrix size is #define'd.
>>> panic: Page table fault when accessing virtual address 0
>>> @ tick 20270000
>>> [invoke:build/ARM/sim/faults.cc, line 70]
>>> Memory Usage: 199008 KBytes
>>> Program aborted at tick 20270000
>>> Aborted (core dumped)
>>>
>>>
>>> I need help of u guys to find out reason for the error. Please note
>>>that
>>> I
>>> have checked the file m5out/stat.tx, but this file is empty when the
>>> error
>>> appears.
>>>
>>> Thank you all in advance
>>>
>>>
>>> Naveed Ul Mustafa
>>>
>>> _______________________________________________
>>> gem5-users mailing list
>>> gem5-users@gem5.org
>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>>
>>
>
>
>Naveed Ul Mustafa
>
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