Hello,
I'm interested in a cycle-accurate simulation of a cluster of nodes, each with
their own CPU/RAM+OS and assocaited network connections. It looks like gem5 can
do this according to
http://www.m5sim.org/Interconnection_Network
and
https://lists.cs.wisc.edu/archive/gems-users/2012-March/msg0
Hi, Zhiguo, Thanks for the reply.
The download link for the original splash2 doesn't work. I tried the one
from the wiki document and compiled and passed the test on native machine.
But the ALPHA version of splash2 (Ocean and FFT) failed to run on Gem5
(OOO, with cache). There are segmentation fa
On Wed, 24 Oct 2012, Cookie wrote:
Hi Nilay,
Thank you for your reply. In MESI_CMP_directory-L1cache.sm, there are
several latency parameters: l1_request_latency, l1_response_latency, and
to_l2_latency. Do you mean these parameters decide the communication time?
However, I didn't see any differ
On Wed, 24 Oct 2012, Malek Musleh wrote:
Hi Nilay,
Yes I agree with those comments, which I is why I posted my question
in the first place because it seemed a bit odd to have to prefetchers
enabled/issued from the sequencer.
Like I said, I have gotten the M5 prefetchers to work with ruby
issui
On Wed, 24 Oct 2012, Runjie Zhang wrote:
Hi, Nilay
I agree with you that to fetch from icache every cycle, hit latency
don't have to be zero.
Here is a snap shot from the exec trace: (deleted some detail to
make it more clear) Icache hit latency is 1 cycle and fetch width is 4
(Ticks)
...60
Thanks for the reply, Hossein, I will try that too.
Best,
On Thu, Oct 25, 2012 at 1:06 AM, Hossein Nikoonia wrote:
> also see Parsec 3.
> It is still in beta; it includes splash2 and splash2x.
>
> Best
> Seyed Hossein
>
> On Thu, Oct 25, 2012 at 7:24 AM, GE ZHIGUO wrote:
>
>> You might want to
Sorry for the confusion.
The numbers 60, 65 and 70 were part of the tick number each cycle started. I
removed some digits in the tick count to make each line shorter...
The complete trace looks like this:
33922322296000: system.switch_cpus.fetch: Running stage.
33922322296000: system.switch_cpus
Hi All,
It seems to me that some of the tournament branch predictor parameters
are redundant, at least given how the predictor is currently
implemented. Has anyone else run into this?
Specifically, the tournament predictor takes nine parameters that can be
configured independently:
localPre
Hello gem5 users,
as I stated 3 days ago, I am new in gem5 world. I installed gem5 and my
goal was to run ffmpeg application inside of SE mode. I realize that I
would have to implement few systemcalls which are not really naive. So, I
talked with my research team and we realized that we can deploy
Hi Marko,
That seems like a good idea. Feel free to create a page
on the wiki and start to populate it.
Thanks,
Ali
On 25.10.2012
11:48, Marko Zivkovic wrote:
> Hello gem5 users,
>
> as I stated 3
days ago, I am new in gem5 world. I installed gem5 and my goal was to
run ffmpeg applic
Hi Erik,
I posted a patch last night that fixed some issues with
the local predictor, but it all certainly could be cleaned up. We'd be
very happy to commit patches that clean up and parameters and code to
address the issues you've identified.
Thanks,
Ali
On 25.10.2012
11:31, Erik Tomusk
Hi,
I am a newbie to gem5. Does the attribute, numThreads in BaseCPU.py and its
corresponding CPU class indicate the number of issue ways of a superscalar
processor? The description in the script explains it is the no of HW thread
contexts. Please correct me if i am wrong.
Thank you
I would like to. Before I do that, I need an input from people who already
ran SE simulations.
Please, just send me the name of the app/benchmark which you successfully
simulated in SE, with and without patches.
Thank you
On Thu, Oct 25, 2012 at 11:23 AM, Ali Saidi wrote:
> **
>
> Hi Marko,
>
Actually I want to set one checkpoint per 1000 instructions.
Can I implement this?
Thanks
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Dear All,
I use following command to run the simulation,
./build/ALPHA_FS/m5.opt ./configs/example/fs.py --detailed --caches --l2cache
--checkpoint-restore=1 -n 1
I want to get CPU utilization rate from stats.txt.
I find there is two values
system.switch_cpus.numCycles 143004
yes.
If you want to change issue width, have a look at issueWidth in o3/O3PU.py
--
Regards,
Mahmood
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system.switch_cpus.idleCycles seems to be a new stat because I don't
have that in my stats.
If you are talking about "unscheduled due to idling", then I think you
should look at idle cycles at IEW stage. If cpu is idle in decode
stage, are you going to include that?
--
Regards,
Mahmood
__
If you search the list archive, you will find the benchamrks (from
spec2k6) that are not runnable in SE mode. I think those syscalls for
x86 are still unimplemented expecially the ones needed for CFP
benchmarks. Some can be bypassed by simply ignoring the syscall or
borrowing from ALPHA.
--
Regar
I agree. I am reading posts and trying to simulate some of them, but it
seems like a waste of time.
We should seriously do something about the syscall implementation or gem5
x86 SE will be retired function. At least, we should summarize the apps
which people were able to deploy.
I quit with SE, I
I am trying to simulate ffmpeg with fs mode. I downloaded x86 image and
binaries, set the paths towards them ( this fixed can't find system path
problem ).
I followed tutorial:
/work/gem5] mount –o loop,offset=32256 linux-x86.img /mnt
[/work/gem5] ls /mnt
bin boot dev etc home lib lost+foun
Hi Marko,
Ensure you have unmounted the disk image.
Also, as the message suggest, you should specify a kernel to use (if I remember
correctly and there is no default for x86).
Good luck.
Andreas
From: Marko Zivkovic mailto:mzivk...@hawk.iit.edu>>
Reply-To: gem5 users mailing list
mailto:gem5
Hello,
I simulated Parsec2.1 benchmark suites with X86_MOESI_hammer and O3 cpu.
I also dumpreset stats frequently to monitor processor activity.
When I simulate only 1 core, things look fine but when I go to multi
cores, some cpus, not all, reports nan values. Does this indicate the cpu
is id
Yes, you can run them. The segmentation fault is due to cache alignment problem
in the source code.
You can modify a little bit to solve the problem. You can search through the
internet to get the solution.
Regards,
Zhiguo
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] O
Hi All,
I am looking into the fetching stage for X86 O3. I have one question. For
ordinary PC advancing without prediction or branch, lets say the current PC
is:
0x4120a4.0 while the nextPC associated with the same DynInst is 4120a5.1
Why the actual PC fetched next will be 0x4120a4.1 instead of 41
One more question will be is the nextPC associated with the DynInst the
physically next instruction stored after the current one, or it is just
predicted by some units??
On Thu, Oct 25, 2012 at 8:14 PM, Shen Yiran wrote:
> Hi All,
>
> I am looking into the fetching stage for X86 O3. I have one q
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