Hi Jaishankar,
If you really want to do a power-controlled Linux-scheduler then it sounds more
like a PhD thesis (or two) to me :)
Currently, there is no on-line power model in gem5, so this is the first thing
to address, and this applies to CPU, caches, interconnect, DRAM, I/O etc. The
power
Hi,
I have a question about implementing prefetching with the Ruby Memory
Model. Looking at the Sequencer.cc code, there is a comment about how
hardware prefetches should be issued in the makeRequest() routine.
Now, I can sort of understand why hardware prefetches should be issued
from the sequenc
Paul V. Gratz gratz1.com> writes:
>
> Thanks Tony! I'd like to get a copy of your patches for ARM if/when
> you get a chance, though my first interest is x86 at the moment.
>
> Did you hit any other roadblocks in getting the JRE up and running on
> ARM? We'd like to run the JRE on x86, follow
Hello Everyone,
I am trying to clean and/or invalidate all cache lines during a drain. I
think I would need to iterate through every cache block and call
writebackBlock() to put them in the writeback buffer. Anybody have any
suggestions on how to do this? I.e., how to prevent drain from completing
Hello,
I am wondering if there is any documentation on installing java/jre
for x86 disk images? I tried following the instructions for ARM, but I
am guessing that is dependent on booting Ubuntu?
All help is appreciated.
Thanks,
Manu
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Hi,
I have a question about the data fetched from main memory. As in
MESI_CMP_directory-L2cache.sm, action "ee_sendDataToGetXRequestor' sends
the cache block (phyaddr and real data) to the requestor. It also prints
out the debug information as " DPRINTF(RubySlicc, "Address: %s,
Destination: %s, Da
Hi:
Could someone tell me, which source file deals with writing simulation results
into gem5/m5out/stats.txt?
Thanks a lot
Tianwei
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Hi,
I am sorry but I was wrong for the 1st question. When I run the simulator
long enough it started printing out data blocks with real value. So I think
the all-zero information is not the real simulation.
But I still have the 2nd question. When I set my system as 2-core CMP,
MESI_CMP_directory
Hi Yingying,
NetDest indicates in which of the Memory Caches the address is present
in the protocols MachineType. In the case for MESI there are 4:
(L1Cache, L2Cache, Directory, DMA).
[NetDest (4) 0 1 - 0 0 - 0 - 0 - ]
In this case the tag is present only in the second L1Cache (L1Cache1)
[N
Hi, I'm Joosung Lee.
I'm sorry for bothering you to send a similar mail.
But I'm eagerly wanna know about the way to port my own app on the gem5.
I'm trying to run my own application on Android Gingerbread with gem5.
I mounted ARMv7a-Gingerbread-Android.SMP.mouse.nolock.clean.img and put my
apk f
I think I figured out that my own application not even started.
The screen lock which I seen was just came out by the time-out, I guess.
I type the ps instruction in the terminal.
However, there were not exist my own application.
The output below shows the ps results.
USER PID PPID VSIZE RS
Hey
Is this some generic problem with gem5 or I am doing something wrong??
Simulation is doing good for default input parameters but when I am
specifying parameters then following error is coming again and again.
command line: build/ARM/gem5.opt --outdir=bbench2 configs/example/fs.py -
I typed "am start" instruction directly on the terminal.
Then I got the message below.
# am start -a android.intent.action.MAIN -n
com.example.helloworld/com.example.helloworld.MainActivity
Starting: Intent { act=android.intent.action.MAIN
cmp=com.example.helloworld/.MainActivity }
Error type 3
Err
Hi Malek,
Thank you for your explanation. I still have a question. As you said,
[NetDest (4) 0 1 - 0 0 - 0 - 0 - ]
In this case the tag is present only in the second L1Cache (L1Cache1)
Why the tag is only in L1cache? Based on the MESI protocol (inclusive cache
hierarchy), a block in L1 cache
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