Hi, I have a question about implementing prefetching with the Ruby Memory Model. Looking at the Sequencer.cc code, there is a comment about how hardware prefetches should be issued in the makeRequest() routine. Now, I can sort of understand why hardware prefetches should be issued from the sequencer (not necessarily where that comment is placed), because that is the way normal cpu request get issued to ruby.
In view of that, I have ported over the existing gem5 prefetcher models (tagged, stride, ghb) from the Classic Memory to work with Ruby. From initial testing it seems to work fine, but the issue I have is that this only applies for L1 prefetching. Now, does it really make sense to implement prefetching at the L1 level different than the L2? Wouldn't it make sense that the cacheMemory Module perform the prefetch->notify() and scheduke/issue the prefetches in all cases perform? In otherwords, is the comment I am referring to still valid, and what is the main justification for having it issued from that location? Malek _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
