[gem5-users] Shared Multiprocessor Simulation

Hi All in Shared Multiprocessor Simulation, I understood that simulator assigns sequencer to each process, but I need to grab exact flow, I want to understand how shared variables are used, and how data flow between these processors. (In detail : How virtual/physical page mapping is maintained in s

[gem5-users] Is it compulsory to Work with GEM5 we must be expert in Python

Before writing to this I have remember one sentence of one guy we don't have enough time to teach, you have to do your self but I am stuck to move on second so again writing you guys.   What are  the prerequisites  to work GEM5. I am thankful for your kind help. I started GEM5 half a year ago bu

[gem5-users] inifile.cc complation problem

I suddenly have this problem. Since my last build, all I've done is try to sort out the "type" and "system" variables in my platforms. Yet it looks like the build system is detecting the wrong configuration somehow. Any ideas? Thanks Robert. g++34 -o build/ARM/base/inifile.o -c -pipe -fno-str

Re: [gem5-users] Problems with McPAT and gem5

Hi Hongyuan, From my personal experience, tool #1 has been broken for quite some time and when I looked at it, it was far too complicated for me to reverse-engineer and fix. I've had much more success with #2, but for various reasons, I can't make my updated version available yet. It probabl

Re: [gem5-users] inifile.cc complation problem

Hi Robert, It looks like you're trying to use gcc 3.4 to compile the simulator. We don't support anything older than 4.3. Ali On 05.10.2012 06:50, Robert PINSKER wrote: > I suddenly have this problem. Since my last build, all I've done is try to sort out the "type" and "system" variables

[gem5-users] Cache Hit & Miss latencies

Can somebody help me find where to set cache memory parameters? For the time I care about Hit & Miss latencies etc... I use ALPHA ISA in fs mode and I run the splash2 benchmarks with ruby memory system. Thanks in advance! Pavlos ___ gem5-users mailing

Re: [gem5-users] Cache Hit & Miss latencies

Try looking at the Caches.py and CacheConfig.py files. -Tony On Fri, Oct 5, 2012 at 9:27 AM, Pavlos Maniotis wrote: > Can somebody help me find where to set cache memory parameters? > For the time I care about Hit & Miss latencies etc... > I use ALPHA ISA in fs mode and I run the splash2 benchma

Re: [gem5-users] Cache Hit & Miss latencies

In configs/ruby/, there are several configuration files for each coherence protocol (i.e., MESI_CMP_directory.py). The cache latency is set in those files. Actually, the base class RubyCache has several latency parameters you can use(i.e., dataAccessLatency, tagAccessLatency). See its definitio

Re: [gem5-users] Cache Hit & Miss latencies

Hi Anthony, I think these two files are limited to the classic memory system but not Ruby. Tao On 10/05/2012 09:29 AM, Anthony Gutierrez wrote: Try looking at the Caches.py and CacheConfig.py files. -Tony On Fri, Oct 5, 2012 at 9:27 AM, Pavlos Maniotis > wrote:

Re: [gem5-users] inifile.cc complation problem

Yes, I read that problems arose with gcc 4 and that 3.4 was easier. Obviously out of date information. I'll try a more up to date version. Thanks for your quick reply. Robert. ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/

Re: [gem5-users] Cache Hit & Miss latencies

Thanks for the reply. I have already looked at Caches.py and CacheConfig.py but there is only one variable called "latency". I am looking for a more complete and accurate way to configure cache behavior. Pavlos On Fri, 2012-10-05 at 09:40 -0400, Tao Zhang wrote: > Hi Anthony, > > I think thes

Re: [gem5-users] Cache Hit & Miss latencies

In case you didn't see my previous email, I paste it again. In configs/ruby/, there are several configuration files for each coherence protocol (i.e., MESI_CMP_directory.py). The cache latency is set in those files. Actually, the base class RubyCache has several latency parameters you can use(

Re: [gem5-users] Cache Hit & Miss latencies

Thank you very much! Very helpful info! Pavlos On Fri, 2012-10-05 at 09:35 -0400, Tao Zhang wrote: > In configs/ruby/, there are several configuration files for each > coherence protocol (i.e., MESI_CMP_directory.py). The cache latency is > set in those files. Actually, the base class RubyCach

[gem5-users] Assertion failures with java and NPB benchmarks w/ ARM ISA

Hi, I am running some java benchmarks (DaCaPo, SPEC JVM, SPEC JBB and NPB) with the ARM ISA and am receiving assertion failures my commandline ./build/ARM/m5.opt configs/example/fs.py --kernel=vmlinux-3.3-arm-vexpress-emm-pcie --machine-type=VExpress_EMM --disk-image=arm-ubuntu-natty-headless-jav

Re: [gem5-users] Assertion failures with java and NPB benchmarks w/ ARM ISA

Hi Manu, I don't know why you're seeing that issue,but you'd need to provide a back trace to see which event is being scheduled that was already scheduled. FYI, people normally boot with a simple CPU, take a checkpoint, and then restore from that checkpoint. THis lest you get to the region of

Re: [gem5-users] Questions on gem5 and SystemC, IP modeling, and architectural analysis.

Hi Steve, Thanks for your reply, I will try to answer some of your questions/comments now, and may have more later. My interest in SystemC compatibility mainly has to do with its popularity. There are other tools we're interested in that depend on it, and many vendors are able to supply functi

Re: [gem5-users] Assertion failures with java and NPB benchmarks w/ ARM ISA

Ali Saidi umich.edu> writes: > > > Hi Manu, >   > I don't know why you're seeing that issue,but you'd need to provide a back trace to see which event is being scheduled that was already scheduled. FYI, people normally boot with a simple CPU, take a checkpoint, and then restore from that ch

Re: [gem5-users] Assertion failures with java and NPB benchmarks w/ ARM ISA

Hi Manu, A gdb backtrace. Thanks, Ali On 05.10.2012 10:34, Manu Awasthi wrote: > Ali Saidi umich.edu> writes: > >> Hi Manu, I don't know why you're seeing that issue,but you'd need to provide a back > > trace to see which event is being scheduled that was already scheduled. FYI, >

Re: [gem5-users] Did not run benchmark on gem5

Hello Nilay, Thank you very much for your response. Please see this? Here is another program but same message. Those program from benchmarks2 that means multiprogram. What is happening  here? back trace is below: cubic.c  lmssim.txt duff loop3 his

Re: [gem5-users] Did not run benchmark on gem5

On Fri, 5 Oct 2012, Musharaf Hussain wrote: Hello Nilay, Thank you very much for your response. Please see this? Here is another program but same message. Those program from benchmarks2 that means multiprogram. What is happening  here? back trace is below: cubic.c  lms

[gem5-users] Problem with Mesh configuration

Hi all, I've built a system for PROTOCOL=MESI_CMP_directory, on the latest stable tree (changeset: 9073:f75ee4849c40). The post-build tests have failed, and I can't get the system running for the Mesh topology for: ./build/X86/gem5.debug configs/example/ruby_random_test.py --num-cpus=2 --num-dirs=

[gem5-users] Question on runing static benchmarks by power pc

Hi Andreas and All I want to run static benchmarks by POWER pc architecturer. All of those are run by ARM pc Architecturer. When I run one of those as like fac.c by POWER pc made the below messagges. Question here my command is correct or not ? Please back tracing: adpcm.c duff  fa

Re: [gem5-users] problem in running multiple SAME sepc2006 benchmarks under SE mode

I think it's a very good finding. I also had the same issue (instant exit after fast-forward when running multiple processes in SE) and I had a local fix using the same idea (filter exit events that are labeled in one tick). Tao, maybe you want to contact gem5-dev to add this patch, though I t

Re: [gem5-users] problem in running multiple SAME sepc2006 benchmarks under SE mode

Yes, Rio. You are right. One variable is enough. I will take a look how to file the patch. Tao On 10/05/2012 05:48 PM, Rio Xiangyu Dong wrote: I think it's a very good finding. I also had the same issue (instant exit after fast-forward when running multiple processes in SE) and I had a loc

Re: [gem5-users] problem in running multiple SAME sepc2006 benchmarks under SE mode

For your information, the patch has been filed to the review board. Tao On 10/05/2012 05:48 PM, Rio Xiangyu Dong wrote: I think it's a very good finding. I also had the same issue (instant exit after fast-forward when running multiple processes in SE) and I had a local fix using the same id

Re: [gem5-users] questions about cache access in ruby

On Thu, 4 Oct 2012, Cookie wrote: Hi, I have some questions about the cache access in Ruby. As shown in file src/mem/protocol/MESI_CMP_directory-L1.sm: in_port(mandat

Re: [gem5-users] Problem with Mesh configuration

On Fri, 5 Oct 2012, Yaman wrote: Hi all, I've built a system for PROTOCOL=MESI_CMP_directory, on the latest stable tree (changeset: 9073:f75ee4849c40). The post-build tests have failed, and I can't get the system running for the Mesh topology for: ./build/X86/gem5.debug configs/example/ruby_ran