I'm no ARM expert, but typically if page table entries are written (to
update dirty bits) it's more of a write-through than write-back operation.
Steve
On Thu, Nov 20, 2014 at 2:52 PM, Jack Harvard
wrote:
> Steve,
>
> A further question on TLB walker caches, they don't get any writes,
> but the
Steve,
A further question on TLB walker caches, they don't get any writes,
but they they have writebacks, which are only for evicted dirty lines
or uncached writes? It's ARM FS mode running BBench.
Jack Harvard
On Tue, Oct 7, 2014 at 9:22 PM, Steve Reinhardt via gem5-users
wrote:
> Yes, in FS
Yes, in FS mode the OS is the only thing that manages the page tables.
Just like a real system.
On Tue, Oct 7, 2014 at 9:28 AM, mohammad reza Soltaniyeh <
m.soltani...@gmail.com> wrote:
> I am talking about FS mode. I couldn't get the point about page-table
> walker used in gem5. Is it bulky at t
I am talking about FS mode. I couldn't get the point about page-table
walker used in gem5. Is it bulky at the moment ?! In other words, OS is
the only page table manager in FS mode.?! I've seen you add PageTableEntry
to the new released code! But I could not guess what is the reason behind
that.
Are you talking about SE or FS mode? In SE mode, typically the
ISA-independent PageTable class is used to hold the page tables, and no
walker is needed. In FS mode, the page tables are constructed in the
simulated physical memory by the OS running on the simulated platform; we
use the page-table
