Re: [gem5-users] cache statistics

2014-03-03 Thread Fernando Endo
uo >>> >>> -Original Message- >>> From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] >>> On Behalf Of Summer >>> Sent: Wednesday, February 12, 2014 3:01 AM >>> To: gem5-users@gem5.org >>> Subject: [gem5-users] ca

Re: [gem5-users] cache statistics

2014-02-12 Thread Summer
: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On Behalf Of Summer Sent: Wednesday, February 12, 2014 3:01 AM To: gem5-users@gem5.org Subject: [gem5-users] cache statistics Hi all, I am working on a project to improve the last level cache performance and we want to simulate 4

Re: [gem5-users] cache statistics

2014-02-12 Thread Summer
cache miss rate? Zhiguo -Original Message- From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On Behalf Of Summer Sent: Wednesday, February 12, 2014 3:01 AM To: gem5-users@gem5.org Subject: [gem5-users] cache statistics Hi all, I am working on a project to improve the

Re: [gem5-users] cache statistics

2014-02-12 Thread GE ZHIGUO
, 2014 3:01 AM To: gem5-users@gem5.org Subject: [gem5-users] cache statistics Hi all, I am working on a project to improve the last level cache performance and we want to simulate 4 levels of cache in gem5. However, when I simulate using SPEC CPU 2006 on 1 timing cpu, higher associative L4 turns

[gem5-users] cache statistics

2014-02-11 Thread Summer
Hi all, I am working on a project to improve the last level cache performance and we want to simulate 4 levels of cache in gem5. However, when I simulate using SPEC CPU 2006 on 1 timing cpu, higher associative L4 turns out higher miss rate. For example, a 256MB, 32 associative L4 gets miss ra