Hi all,
I am working on a project to improve the last level cache performance
and we want to simulate 4 levels of cache in gem5. However, when I
simulate using SPEC CPU 2006 on 1 timing cpu, higher associative L4
turns out higher miss rate. For example, a 256MB, 32 associative L4 gets
miss rate 38.7% while 256MB, direct mapped L4 gets miss rate 20%. I am
pretty confused by this result but I have tried several runs and got the
same results.
Does anyone have any idea about this?
Your help is greatly appreciated!
Best Regards
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