Hello Pedro,
From the microarchitecture side, it is an implementation choice, and
both (2x128 or 1x256) would be valid, each likely having its own
complications. From the gem5 perspective, I am not sure why it was
implemented this way, maybe this is simply representative of how most
ARM micro
Hi all, follow-up question.
In ARMv8, the LDP instruction:
LDP , , [{, #}]
Will load a pair of 128-bit values (256 in total) from memory to two Q
registers (128-bit vector registers).
When I run debug gem5 to see how the said LDP instruction operates (in
AtomicCPU, for now), I see that it is
Hi Jason,
First of all, thank you for your time and answer. I really appreciate it.
I'll go through the repository that you mentioned, it looks like a promising
source to get inspiration from.
Also, thanks for your support! I think I'm starting to understand the flow of
adding instructions now
Hi Pedro,
I am not as familiar with adding/modifying registers in gem5, but there was a
paper a few years ago called InvisiSpec where they added a hidden buffer and
their gem5 code is public on GitHub:
https://github.com/mjyan0720/InvisiSpec-1.0
Not sure if it is similar to what you are trying
