Hi Samuel,
Thanks a lot for your reply. Sorry for the late reply.
In fact, I was able to locate the file(s) you referred me to before sending
my question. My concern is whether gem5 does/does not support multilevel
TLBs and whether it supports various page sizes.
Thanks.
--
*Best,Abdelrahman H
Hi Abdelrahman,
The TLB is part of the MMU, which is a submodule of the CPU. These
values are specified in the architecture specific source files -- so
in your case, src/arch/x86/X86MMU.py is where the itb and the dtb are
declared. In that file you'll see that the specs for these caches are
define
