Hi Abdelrahman,

The TLB is part of the MMU, which is a submodule of the CPU. These
values are specified in the architecture specific source files -- so
in your case, src/arch/x86/X86MMU.py is where the itb and the dtb are
declared. In that file you'll see that the specs for these caches are
defined there.

Note that if you change these features here, then you will need to
recompile gem5 for them to actualize in your simulation, but it seems
as though the are parameterized, so you can take advantage of that
when the constructors are called.

I hope this helps!

Best,
Sam

On Wed, Aug 10, 2022 at 1:53 AM Abdelrahman S. Hussein
<abdelrahman.sob...@gmail.com> wrote:
>
> Hello,
>
> I am running an x86 Full System Simulation. Looking at the fs.py arguments, I 
> could not find any argument that can let me configure the TLB specifications 
> for my simulation. So, I was wondering if someone would guide me, please, on 
> how to configure it. I took a look at the different related files and 
> scripts, but I could not locate where or how exactly to include these 
> configurations. Below, are the set specifications I would like to apply:
>
> L1 DTLB: 4KB pages: 64-entry, 4-way associative;
>                 2MB pages: 32-entry 4-way associative;
>                  1GB pages: 4-entry fully associative
>
> L1 ITLB: 4KB pages: 128-entry, 4-way associative;
>              2MB pages: 8-entry, fully associative
>
> L2 TLB (D/I) 4 KB pages: 512-entry, 4-way associative
>
>
> So, given that I am simulation in FS mode using fs.py configuration file, 
> would you please guide me on where exactly I should modify or include the TLB 
> specs?
>
> Thanks.
>
> --
> Best,
> Abdelrahman Hussein
> MSc. Student -- Graduate RA/TA
> School of Computing Sciences
> Simon Fraser University, Canada
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