Hello Tiago
Thanks for the info.
Will check out using the "git log ..." command.
Best regards
JO
From: Tiago Muck
Sent: 28 September 2022 12:29
To: The gem5 Users mailing list
Subject: [gem5-users] Re: CHI and GEM5 v22.0.0.2
Hi Javed,
There were several fixes, but not all of
Hi Javed,
There were several fixes, but not all of them had a JIRA ticket. You can check
all fixes:
git log --follow v21.2.1.1..v22.0.0.2 -- src/mem/ruby/protocol/chi/
>From the logs these tickets were fixed:
https://gem5.atlassian.net/browse/GEM5-1180
https://gem5.atlassian.net/browse/GEM5-118
Hello Dr Bruce
Yes, I was referring to the open Jira issues.
OK, I will check the Jira issues for CHI.
Best Regards
JO
From: Bobby Bruce
Sent: 22 September 2022 11:41
To: The gem5 Users mailing list
Cc: Tiago Muck ; Javed Osmany
Subject: Re: [gem5-users] CHI and GEM5 v22.0.0.2
Are you refer
Are you referring specifically to the issues open on the gem5 Jira?
If so, we try to close these issues as they are fixed. So if the issue is
still open, it's likely to still persist. If it's closed, it may not be on
the stable branch yet and only available on the develop branch (it'll be
merged i
Hi Javed,
It seems there is a bug in handling CleanUnique requests. From the code
(src/mem/ruby/protocol/chi/CHI-cache-transitions.sm):
transition({I, SC, UC, SD, UD, RU, RSC, RSD, RUSD, RUSC,
SC_RSC, SD_RSD, SD_RSC, UC_RSC, UC_RU, UD_RU, UD_RSD, UD_RSC},
CleanUnique, BUSY_BLKD) {
Hi Javed,
"setDownstream" expects a list of objects, but it seems you are passing a
list-of-lists. I think in you implementation of CHI_L3Cache you can just change
getAllControllers and getNetworkSideControllers to return self._cntrls directly
because it's already a list.
Best,
Tiago
_
Hello
I have been debugging the assertion failure when the L3$ (residing in the HNF)
clusivity = Mostly Exclusive.
All the failures are related when the config being modelled is L2$ for all CPUs
is private & [L2$, L3$] clusivity == [Mostly Inclusive, Mostly_Exclusive].
Enabling some debug flag
Hello
An update on my previous email...
Have been simulating the multicore system with Parsec/Splash2 benchmarks for
different permutations of clusivity for L2$ and L3$. The results being in the
following table. Note, by L3$, I mean the L3$ within the HNF
L2$ clusivity
L3$ clusivity
Comments
Hello Bobby
It was our local gitlab repository, where the problem resided.
Tks
JO
From: Bobby Bruce [mailto:bbr...@ucdavis.edu]
Sent: 03 March 2022 22:07
To: gem5 users mailing list
Cc: Javed Osmany
Subject: Re: [gem5-users] Re: CHI
Which gitlab repository was this? I don't belie
Which gitlab repository was this? I don't believe we maintain one
officially. The github repo is a mirror of
https://gem5.googlesource.com/public/gem5 so should be up-to-date.
--
Dr. Bobby R. Bruce
Room 3050,
Kemper Hall, UC Davis
Davis,
CA, 95616
web: https://www.bobbybruce.net
On Thu, Mar 3,
Hello
Just an update ...
Previously I had cloned the latest gem5 version (21.2.1.0) from a gitlab
repository (as I was having proxy issues in accessing github). Something must
have gone wrong in the cloning, since that was causing the problem with the CHI
protocol compilation.
I am now able t
Hello
So I thought the reason why my previous command line options were not being
parsed in the latest version of gem5 (21..2.1.0) could be because the CHI.py
and CHI_config.py files were not being compiled when generating the executable
gem5.opt binary.
So I tried the following command:
rm -
Hi,
Prefetch implementation seems unchanged and incomplete since the first release
of the CHI protocol. In particular, the notifyPf* functions in
CHI-cache-funcs.sm are still all empty. I am also not aware of any related open
Jira issues.
Regards,
Gabriel
__
Hello Gabriel
Thank you, once again, for the pointers.
Best regards
J.Osmany
-Original Message-
From: Gabriel Busnot via gem5-users [mailto:gem5-users@gem5.org]
Sent: 27 August 2021 10:53
To: gem5-users@gem5.org
Cc: Gabriel Busnot
Subject: [gem5-users] Re: CHI, Ruby - changing
Hi again ;),
Yes, Ruby should support any cacheline size (at least as long as it is a power
of two).
And yes, you need to change the parameter O3CPU.fetchBufferSize and defaulted
to 64 bytes. Not sure if it has any other implications but O3_ARM_v7a_3 sets it
to 16 for instance.
Regards,
Gabrie
Hello Gabriel
Thank you for the clarification.
Best regards
J.Osmany
-Original Message-
From: Gabriel Busnot via gem5-users [mailto:gem5-users@gem5.org]
Sent: 17 August 2021 09:33
To: gem5-users@gem5.org
Cc: Gabriel Busnot
Subject: [gem5-users] Re: CHI and Ruby Cache block size
Hi
Hi Javed,
First a note about the relationship of classes involved in the CHI model.
The L1 and L2 CHI caches are not derived from python class RubyCache
corresponding to C++ class CacheMemory. CacheMemory is only responsible for
managing the memory of the cache, not the protocol that goes around
bject: [gem5-users] Re: CHI - Cluster CPUs having a shared L2 cache
Hi Javed,
I don't have a reliable answer for you. It is possible that the current CHI
cache implementation cannot be shared, although it would surprise me. I would
suggest you to ping Tiago Mück who wrote this stuff to ask
Hi Javed,
I don't have a reliable answer for you. It is possible that the current CHI
cache implementation cannot be shared, although it would surprise me. I would
suggest you to ping Tiago Mück who wrote this stuff to ask him about that.
On your side, you can dig in the ProtocolTrace flag outp
-inclusive of the upstream L1 caches.
Can you please confirm if this is the case?
Best regards
J.Osmany
_
From: Javed Osmany
Sent: 04 August 2021 08:38
To: gem5 users mailing list
Cc: Gabriel Busnot ; Javed Osmany
Subject: RE: [gem5-users] Re: CHI
rds
J.Osmany
-Original Message-
From: Javed Osmany
Sent: 22 July 2021 11:52
To: 'gem5 users mailing list'
Cc: Gabriel Busnot ; Javed Osmany
Subject: RE: [gem5-users] Re: CHI - Cluster CPUs having a shared L2 cache
Hi Gabriel
Many thanks for your insight and input.
I have ta
ll set the desired name.
Will try this out.
Best regards
J.Osmany
-Original Message-
From: Gabriel Busnot via gem5-users [mailto:gem5-users@gem5.org]
Sent: 22 July 2021 08:40
To: gem5-users@gem5.org
Cc: Gabriel Busnot
Subject: [gem5-users] Re: CHI - Cluster CPUs having a shared L2 cac
Hi Javed,
Woops, I didn't see the split option in your first post. My bad.
I think the l2 is actually named "system.cpu0.l1i.downstream_destinations" and
you will find it in the ini file. I think this is due to the way gem5 sets
SimObject names. When you assign a SimObject to several object att
# Setup data message size for all controllers
for cntrl in all_cntrls:
print ("CHI.py -- Cntrl is %s\n" % (cntrl))
cntrl.data_channel_size = params.data_width
I get the following output:
CHI.py -- Cntrl is .cpu0.l1i
CHI.py -- Cntrl is .cpu0.l1d
CHI.py -- Cntrl is .c
Hi Javed,
addSharedL2Cache is only called on lines 465 and 470 of CHI.py and these lines
are touched only if options.littleclust_l2cache == 'shared'.
You don't set it in the command line and the default value is 'private', which
explains why it never gets called.
Also I suspect that on lines 47
ment the shared L2Cache would be much
appreciated.
Thanks in advance
JO
-Original Message-
From: Javed Osmany
Sent: 12 July 2021 09:29
To: gem5 users mailing list
Cc: Gabriel Busnot ; Javed Osmany
Subject: RE: [gem5-users] Re: CHI - Cluster CPUs having a private L2 cache
Hello Gab
Hello Gabriel
Thank you for your reply. Will realise your suggestions.
Best regards
JO
-Original Message-
From: Gabriel Busnot via gem5-users [mailto:gem5-users@gem5.org]
Sent: 12 July 2021 09:23
To: gem5-users@gem5.org
Cc: Gabriel Busnot
Subject: [gem5-users] Re: CHI - Cluster CPUs
Hi Javed,
This looks fine to me, at least regarding L2s being private.
CHI_config.py:538 in the line where you instantiate a cache memory per CPU and
CHI_config.py:557 is the line where you instantiate the CHI ruby controller
that makes use of that cache memory instance.
One way to check if two
Many thanks for the clarification, Gabriel.
Best regards
JO
-Original Message-
From: Gabriel Busnot via gem5-users [mailto:gem5-users@gem5.org]
Sent: 18 June 2021 17:02
To: gem5-users@gem5.org
Cc: Gabriel Busnot
Subject: [gem5-users] Re: CHI and caches
Hi,
O3_ARM_v7a_3 comes with
Hi,
O3_ARM_v7a_3 comes with predefined cache configurations that correspond to this
specific CPU: O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, etc.
However, these caches are effectively used only if CacheConfig.config_cache()
is called. This does not happen if --ruby is used with the fs.py and se.py
f
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