Hello Gabriel Many thanks for your thoughts.
Just checking, is Tiago's email tiago.m...@arm.com? Best regards J.Osmany -----Original Message----- From: Gabriel Busnot via gem5-users [mailto:gem5-users@gem5.org] Sent: 10 August 2021 09:59 To: gem5-users@gem5.org Cc: Gabriel Busnot <gabriel.bus...@arteris.com> Subject: [gem5-users] Re: CHI - Cluster CPUs having a shared L2 cache Hi Javed, I don't have a reliable answer for you. It is possible that the current CHI cache implementation cannot be shared, although it would surprise me. I would suggest you to ping Tiago Mück who wrote this stuff to ask him about that. On your side, you can dig in the ProtocolTrace flag output. It can be quite easy to read once greped to the cacheline you want. It will tell you how you got into the RU state which violates the strict inclusiveness of the L2 claimed by the CHI_L2Controller class. You could benefit from the RubyGenerated flag as well to trace the actions executed by each controller. Also use --debug-start to reduce trace size and pipe output to gzip to compress it significantly (read with zcat). I have a working patch available to accelerate tracing when piping to gzip but I didn't have time to finalize the tests yet. You can find it here: https://gem5-review.googlesource.com/c/public/gem5/+/45025. Gabriel _______________________________________________ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s _______________________________________________ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
