Hi Andreas,
Thank you so much for the patch and explanation. I will start from there,
really appreciate the help!
Best Regards,
Zheng
On 2013-07-19, at 4:25 AM, Andreas Sandberg wrote:
> It's probably going to be a bit tricky to do this from the CPU class since it
> doesn't know about the s
Hi Zheng,
On 07/18/2013 06:37 PM, Zheng Wu wrote:
I have a system with no last level SHARED cache but each cpu has a PRIVATE last
level cache. For each cpu, i want to monitor the number of cache misses in the
last level (i.e. number of request to main memory). I want to do this on each
cycle/
Hi All,
I have a system with no last level SHARED cache but each cpu has a PRIVATE last
level cache. For each cpu, i want to monitor the number of cache misses in the
last level (i.e. number of request to main memory). I want to do this on each
cycle/tick of the simulation.
Basically, I want t
