Hi All, I have a system with no last level SHARED cache but each cpu has a PRIVATE last level cache. For each cpu, i want to monitor the number of cache misses in the last level (i.e. number of request to main memory). I want to do this on each cycle/tick of the simulation.
Basically, I want to implement a way to query this information from "AtomicSimpleCPU::tick()" function since i am using atomic cpu for simulation. Any ideas how I can get this information? Any help or comments is much appreciated it! Best Regards, Zheng Wu _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
