Hi Manu,
Would it be possible to enable the CachePort, Cache and Bus debug flags
for the last 10 ticks?
Thanks,
Andreas
>
>
>On 10/9/12 8:47 AM, "Manu Awasthi" wrote:
>
>>> Hi Manu,
>>> A gdb backtrace.
>>>
>>> Thanks,
>>> Ali
>>
>>Ali,
>>Attached is the gdb backtrace for DaCaPo/lusearch
>
> Hi Manu,
> A gdb backtrace.
>
> Thanks,
> Ali
Ali,
Attached is the gdb backtrace for DaCaPo/lusearch
#0 0x003630e30285 in raise () from /lib64/libc.so.6
#1 0x003630e31d30 in abort () from /lib64/libc.so.6
#2 0x003630e29706 in __assert_fail () from /lib64/libc.so.6
#3 0x000
Hi Manu,
A gdb backtrace.
Thanks,
Ali
On 05.10.2012 10:34,
Manu Awasthi wrote:
> Ali Saidi umich.edu> writes:
>
>>
Hi Manu, I don't know why you're seeing that issue,but you'd need to
provide a back
>
> trace to see which event is being scheduled that was
already scheduled. FYI,
>
Ali Saidi umich.edu> writes:
>
>
> Hi Manu,
>
> I don't know why you're seeing that issue,but you'd need to provide a back
trace to see which event is being scheduled that was already scheduled. FYI,
people normally boot with a simple CPU, take a checkpoint, and then restore
from
that ch
Hi Manu,
I don't know why you're seeing that issue,but you'd need
to provide a back trace to see which event is being scheduled that was
already scheduled. FYI, people normally boot with a simple CPU, take a
checkpoint, and then restore from that checkpoint. THis lest you get to
the region of
Hi,
I am running some java benchmarks (DaCaPo, SPEC JVM, SPEC JBB and NPB) with
the ARM ISA and am receiving assertion failures
my commandline ./build/ARM/m5.opt configs/example/fs.py
--kernel=vmlinux-3.3-arm-vexpress-emm-pcie --machine-type=VExpress_EMM
--disk-image=arm-ubuntu-natty-headless-jav
