Hi Neha,
That is not an error. Did you specify maximum number of instructions to be
executed in your command line? If so, it just exits once it completes that
many instructions.
Hope this helps.
-Tejasi
On Sat, Oct 12, 2013 at 5:18 PM, Neha Kharwadkar
wrote:
> Hi I have installed gem5 simulato
Hi,
Actually, even I get the same error as Amina but while running in se mode
when I use --fast-forward option.
The command line I am using is:
./build/ALPHA_MESI_CMP_directory/gem5.opt configs/example/se_modular.py -n
16 --cpu-type=detailed --clock=1GHz --topology=MeshDirSolo --caches
--cachelin
Hi All,
I am getting the following error when I try to run gem5 with the command
line mentioned below-
fatal: Ruby functional read failed for address 0x581bb000
@ cycle 4377668000
[recvFunctional:build/ALPHA_MESI_CMP_directory/mem/ruby/system/RubyPort.cc,
line 270]
my command line-
./build/ALP
Hi All,
I need to schedule a call to a function every n number of cycles in
Sequencer.cc. I tried to use schedule function to do that but it fails.
Could anyone please explain to me how to schedule calls to functions every
specific number of cycles(like wakeup() is scheduled)? Also, please let me
spilled back to memory.
>
> Ali
>
>
>
> On 18.04.2013 13:40, tejasi pimpalkhute wrote:
>
> Hi All,
>
> I am running splash2 benchmarks in SE mode and I am getting the number of
> write requests to the memory controller as 0 for all the benchmarks.
>
> m
Hi All,
I am running splash2 benchmarks in SE mode and I am getting the number of
write requests to the memory controller as 0 for all the benchmarks.
memory_writes: 0
Sample command line which I am running is:
./build/ALPHA_MESI_CMP_directory/gem5.opt configs/example/se.py -n 16
--cpu-type=det
mailing list
> Date: Thursday, 28 March 2013 00:59
> To: gem5 users mailing list
> Subject: Re: [gem5-users] fatal: SimpleDRAM system.physmem is unconnected!
>
> Hi Tejasi,
>
> To my knowledge, SimpleDRAM and SimpleMemory cannot work with Ruby
> directly. please
Hi All,
I am trying to run se.py using SimpleDDR3 in place of SimpleMemory and I am
getting the error-
fatal: SimpleDRAM system.physmem is unconnected!
The command I am running is:
./build/ALPHA_MESI_CMP_directory/gem5.opt configs/example/se.py -n 16
--cpu-type=timing --clock=1GHz --topology=M
Hi All,
Could anyone please tell me if I can check the count of L1 cache miss at
runtime, say after x cycles? The cache profiler has the record of all the
cache misses but is there any way I can get the information from it at
runtime and pass it to its router/NI?
Also, I wanted to know if the dat
Hi,
I am trying to run Parsec benchmark using ruby full system. I have taken
all the files from the parsec-m5 website and followed the guidelines
mentioned in the document. However, I am getting an error *panic: Error
opening /dist/m5/system/disks/linux-parsec-2-1-m5.img* on running the
following
Hi ,
I am trying to run ruby_fs.py on the latest gem5 version. The command I
used is as follows-
./build/ALPHA/gem5.opt configs/example/ruby_fs.py -n 4 --ruby
--garnet-network=fixed -b ValMemLat --cpu-type=timing
However, I am getting this error-
fatal: Functional write not implemented.
@ cycl
34 AM, Andreas Hansson wrote:
> Hi Tejasi,
>
> It seems you are using a rather old version of gem5. I'd suggest trying
> a more recent version before digging any further.
>
> Andreas
>
> From: tejasi pimpalkhute
> Reply-To: gem5 users mailing list
> Date: F
Hi ,
I am trying to run Splash2 benchmark on SE mode using the following command-
./build/ALPHA_SE/gem5.opt configs/splash2/run.py -n16
--rootdir="v1-splash-alpha/splash2/codes" --benchmark=FMM
However, I am getting the error-
Program received signal SIGSEGV, Segmentation fault.
0x08066f32 in B
ation? Can you
please clarify this? Thanks for your time.
On Tue, Oct 9, 2012 at 9:14 PM, Nilay wrote:
> On Tue, October 9, 2012 6:16 pm, tejasi pimpalkhute wrote:
> > Thanks, Nilay. I can know the ranks and banks from the physical address
> > (datatype physical_address_t) which I g
for pestering you
with a lot of questions.
Thanks a lot for your guidance.
On Thu, Oct 4, 2012 at 4:22 PM, Nilay Vaish wrote:
> On Thu, 4 Oct 2012, tejasi pimpalkhute wrote:
>
> Thanks a ton for explaining this, I think I was mistaken earlier. In that
>> case, can I know be
implementing a memory-aware arbitration technique at the
router. I appreciate your patience.
On Thu, Oct 4, 2012 at 2:23 PM, Nilay Vaish wrote:
> On Thu, 4 Oct 2012, tejasi pimpalkhute wrote:
>
> Hi Nilay,
>>
>> Thanks for throwing light on this. I want to arbi
, Oct 4, 2012 at 9:46 AM, Nilay Vaish wrote:
> On Tue, 2 Oct 2012, tejasi pimpalkhute wrote:
>
> Hi Tushar,
>>
>> Thanks for looking into the code, I tried running the Network_test
>> protocol
>> and got this error:
>>
>> Global frequency set at 100
t;
> - Tushar
>
>
> On Oct 2, 2012, at 2:34 PM, tejasi pimpalkhute wrote:
>
> Hi Nilay and Tushar,
>
> I got rid of that error by writing a check for memory message and network
> message in the SWallocator_d.cc. However, I am getting a deadlock error now
> wh
obvious error here (method -
priority_arbitrate_outports), I am unable to find out what could have gone
wrong. Thanks for your guidance and time.
On Thu, Sep 27, 2012 at 5:46 AM, Nilay Vaish wrote:
> On Wed, 26 Sep 2012, tejasi pimpalkhute wrote:
>
> Hi Nilay and Tushar,
>>
>
.cc
>> A cast into NetworkMessage has been done in places like RoutingUnit_d but
>> that won't give you the message type.
>> You'll have to dig in and see why the cast fails…
>>
>> - Tushar
>>
>> On Sep 26, 2012, at 2:17 AM, tejasi pimpalkh
Hi,
I tried printing the number of input ports and output ports from
SWallocator.cc using this
*m_num_inports = m_router->get_num_inports(); //return
m_input_unit.size()*
*m_num_outports = m_router->get_num_outports(); *
It prints the values as 4 input ports and 4 output ports. I had read
so
Hi Tushar,
I had resumed working on this again, so was going through your
emails(please see email below). I am still getting this error:
gem5.debug: build/ALPHA_SE_MOESI_hammer/base/cast.hh:49: T safe_cast(U)
[with T = const MemoryMsg*, U = Message*]: Assertion `ret' failed.
Program aborted at cy
Hi Tao,
I am using Rio's DRAMSim2 and Gem5 integration patch for my research. I am
working with GARNET network model and was wondering if this patch supports
GARNET NoC model (you had mentioned earlier that it does not support RUBY
and this is a ruby network model). If not, could you please guide
I mean, can I know which memory specifically is currently configured?
On Fri, Sep 7, 2012 at 12:10 PM, Nilay Vaish wrote:
> On Fri, 7 Sep 2012, tejasi pimpalkhute wrote:
>
> I agree, but I need comparison of different DDR and other alternative
>> memories. Can I print somewhe
I agree, but I need comparison of different DDR and other alternative
memories. Can I print somewhere which memory specifically is currently
configured?
On Thu, Sep 6, 2012 at 11:04 PM, Nilay Vaish wrote:
> On Wed, 5 Sep 2012, tejasi pimpalkhute wrote:
>
> Thanks for your prompt re
Wed, Sep 5, 2012 at 1:34 PM, Nilay Vaish wrote:
> On Wed, 5 Sep 2012, tejasi pimpalkhute wrote:
>
> Hi,
>>
>> Can someone please confirm if the main memory configured in Gem5 is DDR2?
>>
>>
> The classic memory system makes use of a very simple memory contr
Hi,
Can someone please confirm if the main memory configured in Gem5 is DDR2?
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Hi Nilay,
I didn't realise it was your persona email-id, I just did a reply to your
email. Thanks for your help!
On Wed, Jun 13, 2012 at 9:30 PM, Nilay wrote:
> On Fri, June 8, 2012 11:20 pm, tejasi pimpalkhute wrote:
> > Thanks, is there any parameter to know how many cycles ar
I am using the formula- Memory utilization = number of clock cycles used
for data transfer / number of total clock cycles
On Fri, Jun 8, 2012 at 4:48 AM, Nilay wrote:
> On Thu, June 7, 2012 11:36 pm, tejasi pimpalkhute wrote:
> > Thanks, Nilay! So, is Ruby_cycles the total number of c
memory utilization?
On Thu, Jun 7, 2012 at 6:12 AM, Nilay Vaish wrote:
> On Wed, 6 Jun 2012, tejasi pimpalkhute wrote:
>
> Hi Nilay,
>>
>> I want to dump the statistics for memory utilization ( number of clock
>> cycles used for
>> data transfer divided by the num
value can I use
for total cycles of data transfer and also if I can use Ruby_cycles (from
profiler.cc) value for total number of cycles. Could you please guide me on
that?
On Sun, Jun 3, 2012 at 5:48 PM, tejasi pimpalkhute wrote:
> Thanks, Nilay! That helps to get started.
>
>
> O
Thanks, Nilay! That helps to get started.
On Sun, Jun 3, 2012 at 5:47 PM, Nilay Vaish wrote:
> On Sun, 3 Jun 2012, tejasi pimpalkhute wrote:
>
> Hi there,
>>
>> I wanted to change the physical memory model for DDR to some other types
>> of
>> memory like
Hi there,
I wanted to change the physical memory model for DDR to some other types of
memory like Phase change RAM or so. Could you please let me know if it is
possible to do so and what all files will I need to touch? (I saw the
specifications for DDR are written in dram(.hh/.cc), do I need to wr
Hi,
I am working on developing an intelligent router that has information of
off-chip main memory at its initialization so that it can give priority to
the request packets based on their bank addresses. Could you please let me
know if it is possible?
I went through the code and saw that the class-
Hi Team,
We are trying to implement an SDRAM aware router that re-orders packets
based on their row address and bank address so as to minimize time.
In order to implement this, we are modifying the code in Swallocator_d.cc
where the packets are re-ordered as per priority. To determine the priorit
Hi,
I have modified memorycontroller.cc (have only one input queue instead of
bankqueues) but I am getting the following error while building it:
expected unqualified-id before 'if'
Has anybody witnessed this error before? What could be the reason for this?
There is no other error (not even a mi
twork=fixed
Please let me know if I am missing something here.
On Mon, Nov 28, 2011 at 6:52 PM, Tushar Krishna wrote:
> Can you send me your file and your command line. Might be faster.
>
> Tushar
>
> On Nov 28, 2011, at 8:29 PM, tejasi pimpalkhute
> wrote:
>
> Hi Tusha
pology file to help
> debug ...
>
> - Tushar
>
>
>
> On 11/26/2011 10:44 PM, tejasi pimpalkhute wrote:
>
> HI Tushar,
>
> I ran the following command:
>
> ./build/ALPHA_SE/gem5.opt configs/example/ruby_network_test.py
> --num-cpus=8 --num-dirs=1 --topology=MeshD
irs=1 in the command line when you ran
> it?
>
> - Tushar
>
>
>
> On 11/26/2011 10:06 PM, tejasi pimpalkhute wrote:
>
> Hi Tushar,
>
> I am trying to create a different topology, similar to mesh but it only
> has 1 director controller node which will be connected
entries:
> Look at src/mem/ruby/network/Topology.cc
> The createLinks function calculates shortest distance between nodes and
> passes this information to makeLinks which in turn calls the makeInLink,
> makeOutLink and makeInternalLink functions in GarnetNetwork_d.cc which then
> calls e
too using the given ones as reference.
> You just need to add a .py file of your topology in the topologies folder,
> and also add it in
> src/mem/ruby/network/topologies/SConscript
>
> Hope this helps,
> Tushar
>
>
>
> On 10/27/2011 4:09 PM, tejasi pimpalkhute wrote:
I really appreciate your help.
On Mon, Nov 14, 2011 at 12:14 AM, Nilay Vaish wrote:
> First a disclaimer, I might wrong in my understanding of gem5. But I will
> still try to answer your questions. The answers are inline.
>
>
> On Fri, 11 Nov 2011, tejasi pimpalkhute wrote:
>
Hi Team,
We are trying to implement An SDRAM aware flow control on Gem5 for which we
need to add some intelligence(i.e., the router schedules the requests based
on Row Address and Bank Address) to the router and thus reduce the
complexity of Memory controller in the Memory Subsystem.
It would be
Hi there,
I am trying to route the memory and non-memory requests separately. Could
you please guide me in differentiating the addresses (e.g. something like
address parser)?
--
Thanks and Regards,
Tejasi
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Hi,
I was looking into the code file Mesh.py in Topology folder and the online
documentation for it says that every node has L1,L2 cache and directories
connected to it. As I had read somewhere, in Gem5, directory controller and
memory controller are same, could you please let me know if Directory
ion
> before and there was a patch attached to one of the answers. Assuming you
> mean DRAMSim 1, there's DRAMSim 2 as well.
>
> On 8 Aug 2011, at 19:13, tejasi pimpalkhute wrote:
>
> > Hi there,
> >
> > I wish to integrate gem5 with DRAMSim for my project. C
Hi there,
I wish to integrate gem5 with DRAMSim for my project. Could you please let
me know where I can find the patch for the same?
--
Thanks and Regards,
Tejasi
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