ps this is not possible in your case, but have you considered
> simply running the code on gem5? It is not obvious to me how you get a
> meaningful multi-core memory trace to be portable between memory systems
> (and even simulators).
>
> Andreas
>
> From: mihai pricopi
>
gt; traces in gem5 using the CommMonitor.
>
> Andreas
>
>
>
> From: mihai pricopi
> Reply-To: gem5 users mailing list
> Date: Wednesday, 11 December 2013 16:57
>
> To: gem5 users mailing list
> Subject: Re: [gem5-users] traffic generator
>
> Hi A
os.
>
> Let me know if there are any other issues along the way.
>
> Andreas
>
> From: mihai pricopi
> Reply-To: gem5 users mailing list
> Date: Tuesday, 10 December 2013 09:43
> To: gem5 users mailing list
> Subject: Re: [gem5-users] traffic generator
>
>
Hi all,
In case anyone else is looking for the answer:
you need to use the script "util/encode_packet_trace.py" to encode the
trace into a proto compatible format.
After that it works.
Regards,
Mihai
On Tue, Dec 10, 2013 at 3:14 PM, mihai pricopi wrote:
> Hi,
>
> I
Hi,
I have been trying to use the traffic generator with the provided trace
files.
I have changed the simple-dram.cfg file into:
STATE 0 100 TRACE tests/quick/se/70.tgen/tgen-simple-dram.trc 100
STATE 1 10 LINEAR 100 0 134217728 64 3 3 0
INIT 0
TRANSITION 0 1 1
TRANSITION 1
ew.py
> src/dev/arm if you want to dig in a bit deeper in the memory maps of these
> systems.
>
> Andreas
>
> On 20/02/2013 05:39, "mihai pricopi" wrote:
>
>>To rephrase, I set the memory size --mem-size=256MB and the
>>pkt->getAddr() or pkt->req-&
d, Feb 20, 2013 at 1:35 PM, mihai pricopi wrote:
> I did that and I noticed that for the VExpress_EMM the L2 cache
> physical addresses are in the 4GB range regardless of the physical
> memory size I set for gem5.
> Is this correct ?
>
> On Tue, Feb 19, 2013 at 8:59 PM, Ali Said
>
> On Feb 19, 2013, at 1:40 AM, mihai pricopi wrote:
>
>> Hi,
>>
>> I am currently tracking the accesses at the L2 cache in an ARM FS
>> mode. I am extracting the physical address by calling the
>> pkt->getAddr() function
>> I am interested in the
Hi,
I am currently tracking the accesses at the L2 cache in an ARM FS
mode. I am extracting the physical address by calling the
pkt->getAddr() function
I am interested in the physical page number of this address. I know
uses variable page size (4 or 5 possible sizes) so I cannot assume
that all
kernel tree.
>
> Ali
>
> Sent from my ARM powered mobile device
>
> On Feb 17, 2013, at 4:16 AM, mihai pricopi
> wrote:
>
> The vmlinux-emm-pcie-3.3.tar.bz2 doesn't contain the kernel source.
> Is it somewhere on that page and I don't see it ?
>
>
> O
The vmlinux-emm-pcie-3.3.tar.bz2 doesn't contain the kernel source.
Is it somewhere on that page and I don't see it ?
On Sat, Feb 16, 2013 at 11:34 PM, Ali Saidi wrote:
> Take a look at http://gem5.org/Download
>
> Ali
>
>
> On Feb 15, 2013, at 9:49 PM, miha
Hi,
Does anyone know where can I obtain the kernel source used for compiling
the latest arm VExpress_EMM kernel image from the download page ?
I have tried to configure myself a linaro-linux.3.3 with the same config
file but the gem5 crashes after intercepting a wrong address on the bus
(0x1c00
Hello,
I am trying to do a functional TLB entry search in FS mode without
modifying any state.
I am using the */arch/arm/tlb.cc TLB::lookup(Addr va, uint8_t cid, bool
functional)* function.
I noticed that this function updates the LRU array regardless of the *
functional* argument value.
Maybe
asterIDs to the
> resource that originated the request ?
>
>
> On Tue, Jan 29, 2013 at 3:58 PM, Mahmood Naderan wrote:
>
>> I think so. However Andreas says MasterID is the right thing
>> http://comments.gmane.org/gmane.comp.emulators.m5.users/13388
>>
>> On 1/27
.users/13388
>
> On 1/27/13, mihai pricopi wrote:
> > In cache_imple.hh access() function, is the returned value of
> > pkt->req->contextId() the id of the core who made the cache request
> > (assuming no SMT) ?
> >
> >
> > On Sun, Jan 27, 2013 at 5:45 AM,
In cache_imple.hh access() function, is the returned value of
pkt->req->contextId() the id of the core who made the cache request
(assuming no SMT) ?
On Sun, Jan 27, 2013 at 5:45 AM, Nilay wrote:
> On Fri, January 25, 2013 10:30 pm, mihai pricopi wrote:
> > Hi,
> >
>
Hi,
I would like to trace only the requests coming from lower level of caches
to the last level of cache indicating the cpu that made that request. I
used debug flag Cache but that contains too much information and I don't
know if it indicates who made the request.
Is there a debug flag for this
Hi,
I am trying to compile the kernel that was used in the latest VExpress_EMM
image. I tried the patch and the config file on a linux-linaro.3.3 but it
did not work. Could anyone recompile a kernel using the latest config and
patch ?
Thanks
___
gem5-u
Hi guys,
I want to use ARM FS with more than 4 cores. I really need 8 cores for my
project.
I am using the machine VExpress_EMM with the kernel from the Download site
(vmlinux-3.3-arm-vexpress-emm-pcie) and the disk image gem5-users@gem5.org.
I understood that there might be a way to make this
ation.
>
> On Mon, Oct 22, 2012 at 8:43 PM, mihai pricopi wrote:
>
>> Hi,
>>
>> I am using arm_detailed SE mode.
>> Is there a simple way to force the branch predictor to do perfect
>> prediction ?
>>
>> Thanks
>>
>>
Thanks Andreas.
On Tue, Oct 23, 2012 at 4:36 PM, Andreas Hansson wrote:
> Mitch is spot on I think.
>
> The latencies are for that specific block, caches, busses, memory
> controllers etc.
>
> Andreas
>
> From: mihai pricopi mihai.pric...@gmail.com>>
> Reply-
ath information from this file.
>
>
> On Mon, Oct 22, 2012 at 9:14 PM, mihai pricopi wrote:
>
>> Thanks.
>> Would be enough to change a bit the lookupAndUpdateNextPC() function such
>> that the return is always false ?
>> I mean changing the:
>>
>&g
time variance issues), you could simply run the
> application twice. Save the branch outcomes from the first run. Then
> re-run the app, with a "predictor" that just uses the branch results from
> the first time you ran the application.
>
> On Mon, Oct 22, 2012 at 8:43 PM, mihai pric
Hi,
I am using arm_detailed SE mode.
Is there a simple way to force the branch predictor to do perfect
prediction ?
Thanks
___
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gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
/etc/mtab: No such file or directory
> Thu Jan 1 00:00:02 UTC 1970
> S: devpts
> Thu Jan 1 00:00:02 UTC 1970
> starting pid 354, tty '': '/sbin/getty -L ttySA0 38400 vt100'
>
> AEL login:
>
>
> I am quite confused what is the "AEL lo
I think the system is still running, try to connect using m5term 3457
from another terminal.
On Thu, May 31, 2012 at 10:18 AM, Bojun Ma wrote:
> Hi All,
> I ran gem5 in ARM FS mode with the disk image and kernel download form
> the gem5 download page, but it seems freeze after a while like t
OK thank you.
On May 30, 2012 9:08 PM, "Nilay" wrote:
>
> On Wed, May 30, 2012 7:54 am, mihai pricopi wrote:
> > Please correct me if I'm wrong but from what I understand from the
> > documentation the interconnection network is tiled fashioned. That means
>
s. My concern is that you cannot actually decide the LLC cache into
multiple banks (e.g. 256) and then use garnet to interconnect them. Is this
true?
On May 30, 2012 12:54 PM, "Nilay Vaish" wrote:
> On Wed, 30 May 2012, mihai pricopi wrote:
>
> OK. Do you know how to have acce
OK. Do you know how to have access to the source code of GEMS 1.4 ? I
tried the download website and is not working.
On Wed, May 30, 2012 at 11:51 AM, Nilay Vaish wrote:
> On Wed, 30 May 2012, mihai pricopi wrote:
>
>> I see, thank you.
>> So is it possible to have a multi-bank
29, 2012 at 7:38 PM, Nilay Vaish wrote:
> If you just want to have different latencies for different banks, it seems
> you can make use of Ruby memory system to do that. You may have to modify /
> rewrite some topology file as per your needs.
>
> --
> Nilay
>
>
> On Tue,
Hi all,
Is NUCA supported by gem5 ? If yes, how can I use it ?
Regards,
Mihai
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ecause of the panic. Perhaps you didn't download the entire
> disk image, can't read the disk, etc?
>
>
>
> Ali
>
>
>
> On 23.04.2012 05:44, mihai pricopi wrote:
>
> Hi,
>
> I am new to gem5. I've been trying to run a FS with ARM and no
> s
Hi,
I am new to gem5. I've been trying to run a FS with ARM and no
success. I am using the precompiled binaries and disk image from the
gem5 website. I keep receiving this error:
I think is something to do with the disk image.
Did this happen to anyone ?
./build/ARM/gem5.opt configs/example/f
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