To rephrase, I set the memory size --mem-size=256MB and the pkt->getAddr() or pkt->req->getPaddr() returns for example 0x80007c80. I run the benchmark after creating a checkpoint after booting the system. Would that mean that linux accesses some peripherals mapped at this address ?
On Wed, Feb 20, 2013 at 1:35 PM, mihai pricopi <mihai.pric...@gmail.com> wrote: > I did that and I noticed that for the VExpress_EMM the L2 cache > physical addresses are in the 4GB range regardless of the physical > memory size I set for gem5. > Is this correct ? > > On Tue, Feb 19, 2013 at 8:59 PM, Ali Saidi <sa...@umich.edu> wrote: >> I think you'll have to carry it from the TLB. >> >> Ali >> >> On Feb 19, 2013, at 1:40 AM, mihai pricopi <mihai.pric...@gmail.com> wrote: >> >>> Hi, >>> >>> I am currently tracking the accesses at the L2 cache in an ARM FS >>> mode. I am extracting the physical address by calling the >>> pkt->getAddr() function >>> I am interested in the physical page number of this address. I know >>> uses variable page size (4 or 5 possible sizes) so I cannot assume >>> that all of them are 4K. >>> Is there a way to get it ? or do I have to carry the information from >>> the TLB translation to this level. >>> >>> Thanks >>> _______________________________________________ >>> gem5-users mailing list >>> gem5-users@gem5.org >>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >>> >> >> _______________________________________________ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
