Re: [gem5-users] Problem to run Asimbench

Hi, The problem is caused because the background services of Android are not successfully loaded. You should wait a certain time before executing android applications. Best regards, Yongbing Huang -Original Message- From: gem5-users [mailto:gem5-users-boun...@gem5.org] On Behalf

[gem5-users] How are m5 pseudo instructions implemented?

Hi all, I want to know how the m5 pseudo instructions are implemented, by accessing specific addresses or jumping to specified addresses? I try to integrate these instructions in C++ programs using inline assemble, but don't work. Best regards, Yongbing Hua

[gem5-users] How to convert the implementation of m5 pseudo instructions into GCC inline assembly codes

Hi all, This is the implementation of m5 pseudo instructions. I want to integrate this piece of codes into C++ programs. Can somebody help to translate these codes into the GCC inline assembly codes? .macro simple_op name, func, subfunc .align 2 .globl \name \na

Re: [gem5-users] How to save a file in the disk image?

Hi, You should change the disk model from CowIDE to RawIDE in the FSConfig.py. Best regards, Yongbing Huang From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On Behalf Of 夏飞 Sent: Friday, March 14, 2014 3:40 PM To: gem5-users@gem5.org Subject: [gem5-users]

Re: [gem5-users] Configure the last level cache(LLC) with stt-ram

Hi， Compared to SRAM cache, its access latency is different, which can be easily achieved by modifying the configuration file of cache. However, STTRAM itself may wear out after thousands of accesses. So you need to model this feature of STT-RAM. Gem5 currently doesn’t support this.

Re: [gem5-users] Trace Instruction Flow associated with PID

Hi, I dump the instruction flow before. The patch named inst-trace.patch can be available at https://bitbucket.org/yongbing_huang/gem5-patches/. However, this patch is based on a quite old version of gem5, and the codes are not well organized (not proposed to share). For

Re: [gem5-users] How to calculate memory power using SimpleDRAM module

omate the process and make use of the DRAMPower tool instead. Keep an eye on the review board, and please provide feedback once we get the patches up there. Andreas From: huangyongbing Reply-To: gem5 users mailing list Date: Sunday, 12 January 2014 10:31 To: "gem5-users@gem5

[gem5-users] How to calculate memory power using SimpleDRAM module

Hi all, I want to calculate the detailed power consumed by memory modules. Are there any existing patches or scripts? Thanks. Best regards, Yongbing Huang ___ gem5-users mailing list gem5-users@gem5.org http:/

Re: [gem5-users] How the gem5 executes this rcS script?

Hi, Gem5 will start dumping stats when the music player begin to broadcast the music. Best regards, Yongbing Huang From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On Behalf Of Peng Wei Sent: Tuesday, December 31, 2013 2:15 PM To: gem5 users mailing list

Re: [gem5-users] Problem about Create Checkpoint

Hi Peng, In the AsimBench (renamed as Moby now) image provided by me, there is a rcS file named arm_ckpt_asim.rcS. You can use this file to create the checkpoint. Best regards, Yongbing Huang From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On Behalf Of P

Re: [gem5-users] Usage of CommMonitor

ndreas From: huangyongbing Reply-To: gem5 users mailing list Date: Tuesday, 26 November 2013 09:26 To: "gem5-users@gem5.org" Subject: [gem5-users] Usage of CommMonitor Hi all, I want to use CommMonitor to collect memory trace. I put the CommMonitor between the membus and p

[gem5-users] Usage of CommMonitor

Hi all, I want to use CommMonitor to collect memory trace. I put the CommMonitor between the membus and physmem. The configuration file of CommMonitor is as follows: self.mem_monitor = CommMonitor(trace_file="mem_comm.trace") self.membus.master = self.mem_monitor.slave self.m

[gem5-users] How to view frame buffers

Hi all, I collect a collection of frame buffers using the parameter -frame-capture. But how can I view the output of these frame buffers? Thanks. Best regards, Yongbing Huang ___ gem5-users mailing list gem5-users@gem

Re: [gem5-users] AsimBench: a benchmark suite of Android apps for simulators such as gem5

s for providing everyone with these! Ali On Aug 22, 2013, at 7:46 AM, huangyongbing wrote: Hi all, I have gathered 11 Android applications as a benchmark suite called AsimBench, which cover several categories such as web browser, email, audio, video, document processing and m

[gem5-users] AsimBench: a benchmark suite of Android apps for simulators such as gem5

Hi all, I have gathered 11 Android applications as a benchmark suite called AsimBench, which cover several categories such as web browser, email, audio, video, document processing and map. I also have already ported these applications to the gem5 simulator. Detailed information can be

Re: [gem5-users] Finding the Instruction Mix for a Benchmark

Hi， I notice that in the stat.txt results, the number of executed instructions (iew.iewExecutedInsts) is quite larger than the number of instructions committed (commit.committedInsts) for o3 cpu. For example, 2504310485 for iewExecutedInsts V.S. 1758659165 for committedInsts.

Re: [gem5-users] Micro-TLB in Gem5 ARM model

Hi, To my understanding, separate instruction and data microTLBs are implemented in arm model with 64 entries in default. But the shared MacroTLB is missing. Best regards, Yongbing Huang From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On Behalf Of Ami

[gem5-users] FW: panic: Uncachable load

Hi Ali, The detailed attachment is larger than 128KB, which is forbidden by the mail list. If you need it, I will send it to your mail directly. Thanks! Best regards, Yongbing Huang From: huangyongbing [mailto:huangyongb...@ncic.ac.cn] Sent: Tuesday, June 18

Re: [gem5-users] panic: Uncachable load

27;t clear from the code and I haven't found the behavior to be particularly repeatable to be able to debug it. Ali On May 29, 2013, at 3:06 AM, huangyongbing wrote: Hi Andreas, I am running map and office applications on a modified disk image. I only modify the

[gem5-users] FW: [SPAM] Re: Mismatched stats between gem5 and performance counters when running BBench on ARM platform

...@gem5.org] On Behalf Of huangyongbing Sent: Monday, January 28, 2013 10:11 AM To: 'gem5 users mailing list' Subject: [SPAM] Re: [gem5-users] Mismatched stats between gem5 and performance counters when running BBench on ARM platform Hi Orangeade, Thanks for your reply. I r

Re: [gem5-users] panic: Uncachable load

-users] panic: Uncachable load Hi Yongbing, Could you elaborate a bit on what you are running? For example, is this on an unmodified trunk? If so, how to reproduce it? Thanks, Andreas From: huangyongbing Reply-To: gem5 users mailing list Date: Wednesday, 29 May 2013 07:48 To

[gem5-users] panic: Uncachable load

Hi all, I run the simulator using the arm_detailed CPU model while simulating the ARM platform. However, the bellowing panic will occur sometimes: panic: Uncachable load [sn:4af0382b] PC (0xc016b5c0=>0xc016b5c4).(0=>1) (PC is different for different times, but PCs are often like 0x

Re: [gem5-users] Trace file

Hi, Below is the execution flow of instruction tracer. Hope useful for you. Flow of InstTracer cpu/BaseCPU.py default_tracer = ExeTracer() tracer = Param.InstTracer(default_tracer, "Instruction tracer") cpu/simple/base.cc BaseSimpleCPU::preExecute() traceData = tracer->

Re: [gem5-users] Adding a new benchmark in gem5

Hi, I just port 11 different kinds of applications into the simulator, including music player, video player, map and so on. All of these applications are lack of source codes. I am still testing these applications under different timing models. Maybe images will be public after I compl

Re: [gem5-users] [SPAM] Re: ext2 blocks error while loading from the checkpoint

] Re: [gem5-users] ext2 blocks error while loading from the checkpoint Hi,Yongbin, Do you use armdetailed CPU or timing CPU? Thanks Xiangyang On May 3, 2013 4:24 AM, "huangyongbing" wrote: Hi all, I met problems while booting the simulator from the checkpoint. The e

Re: [gem5-users] ext2 blocks error while loading from the checkpoint

org [mailto:gem5-users-boun...@gem5.org] On Behalf Of huangyongbing Sent: 03 May 2013 09:25 To: gem5-users@gem5.org Subject: [gem5-users] ext2 blocks error while loading from the checkpoint Hi all, I met problems while booting the simulator from the checkpoint. The error shows that “EXT2-fs (s

[gem5-users] ext2 blocks error while loading from the checkpoint

Hi all, I met problems while booting the simulator from the checkpoint. The error shows that "EXT2-fs (sda1): error: ext2_free_blocks: Freeing blocks not in datazone - block = 3856019482, count = 1". By the way, I run the simulator using the ARM platform, and modified the

Re: [gem5-users] how to mount images in Android on ARM platform

form Do you mean when android is running? Because the code below looks like it will attach both to the simulator. Ali On Apr 16, 2013, at 12:33 AM, huangyongbing wrote: Hi all, I create two images for ARM platform using the following codes. But I don't know how to mo

Re: [gem5-users] Pending when executing halt instruction using raw disk

Saidi Sent: Wednesday, April 24, 2013 11:27 PM To: gem5 users mailing list Subject: Re: [gem5-users] Pending when executing halt instruction using raw disk On 24.04.2013 09:07, huangyongbing wrote: Hi all, I want to save the changing of disk image. According to the introduction

[gem5-users] Pending when executing halt instruction using raw disk

Hi all, I want to save the changing of disk image. According to the introduction in http://gem5.org/Bbench-gem5, I boot the simulation using the raw idle disk, and execute "busybox sync" and "busybox halt -f". Then, the system is pending there for several hours. I just modify the image

[gem5-users] how to mount images in Android on ARM platform

Hi all, I create two images for ARM platform using the following codes. But I don't know how to mount the second image into the Android system. Anyone can help? Thanks. self.cf0 = CowIdeDisk(driveID='master') self.cf2 = CowIdeDisk(driveID='master') self.cf0.chil

Re: [gem5-users] How to adjust the window size of VNC

size of VNC Yes. You need to pass a parameter to the kernel otherwise it will default to something that probably isn't what you want. I haven't tried it but vga=788 might solve your problem. Ali On Mar 25, 2013, at 7:43 AM, huangyongbing wrote: Hi, S

[gem5-users] How to simulate the sdcard partition for ARM platform

Hi all, Since applications' data are often stored in the sdcard partition on ARM platform, I want to simulate the file system with sdcard partition. So how should I do? Thanks. Best regards, Yongbing Huang ___ gem5-us

Re: [gem5-users] servicemanager exit on ICS

Sounds great. Thank Chander very much. It is really helpful. Best regards, Yongbing Huang -Original Message- From: Chander Sudanthi [mailto:chander.sudan...@arm.com] Sent: Wednesday, April 10, 2013 12:43 PM To: gem5-users@gem5.org Cc: huangyongb...@ncic.ac.cn; sun...@me.com; hamish...@ya

Re: [gem5-users] How to adjust the window size of VNC

want to change the size of the vnc window you need to change the size of screen that you're simulating (e.g. pass different parameters to the kernel on boot). Ali On Mar 25, 2013, at 3:10 AM, "huangyongbing" wrote: Hi all, I want to adjust the window size of

Re: [gem5-users] questions about checkpoint restore

Hi all, I also try to run 0xbench on gem5. However, when I start the application, it always says that "when an app was designed for a smaller screen, a zoom control will appear by the clock" and stops here. So how to handle it? Thanks. Best regards, Yongbing Huang

[gem5-users] How to adjust the window size of VNC

Hi all, I want to adjust the window size of VNC. On default, it is 1024*768 defined in src/dev/arm/pl111.hh. I simply set the width and height variables in Pl111.write() function, 800*600 for example. However, the output of vncviewer is not correct. Have I missed other things? What sho

[gem5-users] How to get the task_struct entry under arm platform?

Hi all, I want to get the task_struct entry of running process under arm platform in gem5. How can I get the entry? In kernel mode, I can get the thread_info struct by operating the kernel stack pointer stored in the r13 (SP) register. And the task_struct is stored in the

[gem5-users] Triggers to start or stop collecting instruction traces?

Hi all, I want to collect instruction traces belonged to a specific binary. As I know, if some necessary debug flags such as "debug::execenable", "trace:enabled" are set in gem5, the traceInst function will be called and start to collect the instruction traces. So my question is that,

[gem5-users] Doubt about the checkpoint for disk image

Hi all, I want to know that which information about disk image are recorded in the checkpoint files. If I create a checkpoint using image A and then add an application APP1 into image A, whether APP1 is available when I restore from the checkpoint. Thanks! Best regards

Re: [gem5-users] Mismatched stats between gem5 and performance counters when running BBench on ARM platform

Hi Orangeade, Thanks for your reply. I really have done some work to localize the problem. 1) I use arm_detailed mode in gem5. I also close the prefetcher on gem5, the same in real ARM platform. 2) I have already change default 64B cache line into 32B cache line. 3)

[gem5-users] Mismatched stats between gem5 and performance counters when running BBench on ARM platform

Hi all, I recently compared the micro-architectural metrics such as L1 cache miss collected by gem5 with that collected by performance counters on real ARM platform. I found that their difference was so big. For example, the Icache miss rate per 1k instruction of bbench was about 30 co

[gem5-users] Problem when running BBench on ARM platform

Hi all, I run bbench on arm platform using ics image downloaded from gem5's website, and find that bbench stays at the final webpage file:///data/bbench/finish_fifo.html for several hours. So what may be the problem? Thanks. Best regards, Yongbing Huang _

[gem5-users] FW: [SPAM] Re: Compiling Android kernel with PCI support

Hi all, Does anybody solve this problem? Or any ideas? Thanks! Best regards, Yongbing Huang -Original Message- From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On Behalf Of Anirudh Sivaraman Sent: Saturday, June 30, 2012 6:06 AM To: sa...@um

Re: [gem5-users] Faults when booting more than 8 CPUs in X86

when booting more than 8 CPUs in X86 On Mon, 13 Aug 2012, huangyongbing wrote: > Hi all, > > > > I want to simulate a X86 architecture with more than 8 CPUs, > and I recompile the Linux kernel with CONFIG_NR_CPU=16. However, when > I boot the simulator, it gets

[gem5-users] Faults when booting more than 8 CPUs in X86

Hi all, I want to simulate a X86 architecture with more than 8 CPUs, and I recompile the Linux kernel with CONFIG_NR_CPU=16. However, when I boot the simulator, it gets the following message: "Booting processor 9 APIC 0x9 ip 0x6000 APIC never delivered???". The message shows

[gem5-users] How many cores can X86 architecture support

Hi all, I want to simulate many-cores on gem5. So I want to know the maximum cores that gem5 can support for x86 architecture. Thanks. Best regards, Yongbing Huang ___ gem5-users mailing list gem5-users@gem5.org http:

Re: [gem5-users] FW: BBench: What's the connection between port 3456 and 5900

o which CPU model are you using? -Tony On Mon, May 21, 2012 at 7:52 AM, huangyongbing wrote: Hi all, When I running BBench, I notice that port 3456 has already stopped working when the views of port 5900 are still changing. So are there any connections between port 3456 and port

[gem5-users] FW: BBench: What's the connection between port 3456 and 5900

Hi all, When I running BBench, I notice that port 3456 has already stopped working when the views of port 5900 are still changing. So are there any connections between port 3456 and port 5900? If so, the command running in port 5900 should be printed out in port 3456. Do I

[gem5-users] BBench: Why I still met the problem of "fatal: Could not read bootloader"

Hi all, When I try to run BBench on Android using the images provided by the websites, I still met the problem of "fatal: Could not read bootloader". Somebody said in the mail lists that this problem would be fixed. So where is the location of corrected BBench images? Best re

[gem5-users] How to config two different CPUs on a CMP machine?

Hi all, Generally, if there are two CPUs on a CMP machine, both the CPUs are of the same configurations in Gem5. If I want to config two different CPUs with varied cache hierarchies and varied frequences, what should I do in the configuration files? Thanks for advance. --Yongbing Huang _

Re: [gem5-users] Dump trace to file using breakpoints

Hi, To my understanding, there are no interfaces to monitor virtual PC addresses provided by gem5. The most convenient way is instrumentation. -Yongbing Huang From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On Behalf Of Anders Handler Sent: Thursday, Dece

Re: [gem5-users] Problem with Linux kernel 3.1

主题： Re: [gem5-users] Problem with Linux kernel 3.1 I haven't tested this at all (even to make sure it compiles) but give this a shot. This is a quick attempt to actually fix the check. Gabe On 11/28/11 20:35, huangyongbing wrote: Hi, I just tested your patch on my PC (Intel Nehalem),

Re: [gem5-users] Problem with Linux kernel 3.1

_startup_64". Any clue why the simulator gets stuck here? Best regards Anders 2011/11/28 huangyongbing Hi all, I try to run Gem5 using X86_FS and Linux kernel 3.1. The configuration file I use is downloaded from Gem5 website which contained in file 'config-x86.tar.gz'. N

[gem5-users] Problem with Linux kernel 3.1

Hi all, I try to run Gem5 using X86_FS and Linux kernel 3.1. The configuration file I use is downloaded from Gem5 website which contained in file 'config-x86.tar.gz'. No errors are printed out by gem5. However, there is also nothing printed out in m5term console. Using the same configuration fi

[gem5-users] 答复: DRAMsim patch

Hi, I cannot pass the authorization of this link. So can anybody send me a copy of the patch? Or how could I find out my password? Thanks. -邮件原件- 发件人: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] 代表 Malek Musleh 发送时间: 2011年11月1日 12:11 收件人: gem5 users

Re: [gem5-users] rcS and checkpoint restore

I also met the same problem. If I want to do large scale experiments in FS mode with ruby enabled, I have to write all my commands in the rcS file, and boot system each time which cost lots of time. If I use checkpoints, I have to log into the system and input my commands. Thus, it becomes very

Re: [gem5-users] How to enable fast forwarding when ruby module isloaded?

by doesn’t support it. Please refer to http://www.gem5.org/General_Memory_System for the comparison between classic and ruby memory system. -Tao From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On Behalf Of huangyongbing Sent: Tuesday, September 13, 2011 9:21 PM To: gem5-user

[gem5-users] How to enable fast forwarding when ruby module is loaded?

Hi, I want to enable fast forwarding when ruby module is loaded. In the implementation, switching cpu should be happened between AtomicSimpleCPU and TimingSimpleCPU (plus ruby enabled). However, their cache and memory organization are different. What should I do in order to achieve thi

[gem5-users] All requests sent from TimingSimpleCPU to Ruby are in sequential.

Hi, I find that requests from CPU to Ruby are sent in sequential, which means that next request can only be sent after the previous one giving its response to CPU. Thus, if one request needs to access memory, no new request can be sent to ruby during this period. In this way, there no

[gem5-users] All requests sent from TimingSimpleCPU to Ruby are in sequential.

Hi, I find that requests from CPU to Ruby are sent in sequential, which means that next request can only be sent after the previous one giving its response to CPU. Thus, if one request needs to access memory, no new request can be sent to ruby during this period. In this way, there no

[gem5-users] Question about transient states in cache coherence protocol in Ruby

Hi, When compared with other cache coherence protocols, we will find that there exists many transient states in Ruby which complicate state transition. For example, state IS is a transient state in MESI protocol when we transform state I to state S. In other implementation, the state t

Re: [gem5-users] Segmentation fault according to physical memory(Directory_Controller)

It is the same question as the mail "[gem5-dev] Segmentation fault:UnderSituationPhysicalMemory(range=AddrRange("4096MB") and Ruby ". You can find the detailed suituation in this mail. 2011-06-28 --Yongbing Huang 发件人： Nilay Vaish 发送时间： 2011-06-28 11:19:01 收件人： gem5 users mailing list