Hi，
Compared to SRAM cache, its access latency is different, which can
be easily achieved by modifying the configuration file of cache. However,
STTRAM itself may wear out after thousands of accesses. So you need to model
this feature of STT-RAM. Gem5 currently doesn’t support this.
By the way, who is your mentor? I graduated from Wuhan University
as a bachelor.
Best regards,
Yongbing Huang
From: [email protected] [mailto:[email protected]] On
Behalf Of 沈凡凡
Sent: Tuesday, March 11, 2014 10:00 AM
To: gem5-users
Subject: Re: [gem5-users] Configure the last level cache(LLC) with stt-ram
I find that it needs to modify the cache model, so anyone who knows how to
modify the cache model for stt-ram?
Thanks in advance.
Best Regards,
------------------
沈凡凡
Fanfan Shen PhD candidate
Computer School
Wuhan University,Wuhan,Hubei 430072,China
E-mail:[email protected]
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