Hi all,
I'm currently working on the O3 CPU model and want to issue random
instructions in the IWE stage during the readyInsts issuing. It seems like
the program forbids such actions and asserts that the instruction being
issued is the oldest one. Am I looking in the wrong place to do this? Any
he
Hi all,
I'm currently new to the gem5 standard library, and I've used old scripts
for a while which works fine for me. I'd like to know if it is possible to
run a multithreaded program in SE mode with the gem5 standard library. It
seems like the SE workload is not compatible with multithreaded bin
le_with is called with a None object)
>
> Also the script is called FS ruby but you seem to have instantiated a SE
> workload (ArmSeWorkload).
>
>
>
> There’s something wrong in the custom script…
>
>
>
> Kind Regards
>
>
>
> Giacomo
>
>
>
>
Hi all,
I'm currently working on ISA-level tasks and have generated my own binary
using an assembler and linker. The binary executes successfully on my local
environment (M1 ARM). However, when I attempt to run it on gem5, it fails
to be recognized.
I used the following commands to assemble and l
Hi all,
I am currently attempting to obtain information about events between the
MESI_Two_Level L1 cache and L2 cache. Although I have examined protocol
traces, I am seeking additional information about the requestor or original
packet.
For example, the Protocol Traces gives
4541 0L1Cac
Hi all,
I am currently trying to gather cycle information of events and wondering
how I should access CPU cycles in the Ruby port component. It seems like,
although tick is used universally across the simulation, Ruby has its own
cycle setting that is different from the CPU cycle.
Thanks,
Ziyao
_
