[gem5-users] Question on maximum number of outstanding DRAM memory requests that can be generated by a core.

2015-01-18 Thread Prathap Kolakkampadath via gem5-users
Hello Users, Is the maximum number of outstanding DRAM memory requests that can be generated by a core at a time is limited by number of MSHRs in its private cache? For example, In a 4 core system configuration, each core has a private L1 cache with 6 MSHRs each. The systems Last Level cache ha

Re: [gem5-users] DRAMCTRL:Seeing an unusual behaviuor with FR-FCFS scheduler

2014-11-14 Thread Prathap Kolakkampadath via gem5-users
at_same_rank <= min_cmd_at) { >> + if ((bank_mask == 0) || (!switched_cmd_type && same_rank_match && >> +min_act_at_same_rank <= min_cmd_at)) { >> bank_mask = bank_mask_same_rank; >> } >> >> Could you give that a

Re: [gem5-users] DRAMCTRL:Seeing an unusual behaviuor with FR-FCFS scheduler

2014-11-14 Thread Prathap Kolakkampadath via gem5-users
nk_mask_same_rank; > } > > Could you give that a spin? > > Thanks, > > Andreas > > From: Prathap Kolakkampadath via gem5-users > Reply-To: Prathap Kolakkampadath , gem5 users > mailing list > Date: Friday, 14 November 2014 00:11 > To: gem5 users ma

[gem5-users] DRAMCTRL:Seeing an unusual behaviuor with FR-FCFS scheduler

2014-11-13 Thread Prathap Kolakkampadath via gem5-users
Hi Users, For the following scenario: Read0 Read1 Read2 Read3 Read4 Read5 Read6 Read7 Read8 Read9 Read10 Read11 There are 12 reads in the read queue numbered in the order of arrival. Read 0 to Read3 access same row of Bank1, Read4 access Bank0, Read5 to Read8 access same row of Bank2 and Read9

Re: [gem5-users] DRAM memory access latency

2014-11-10 Thread Prathap Kolakkampadath via gem5-users
atency. For the >> precise components included in the various latencies I would suggest >> checking the source code. >> >> Note that the controller is not just accounting for the static (and >> dynamic) DRAM latency, but also the static controller pipeline latency (and &g

Re: [gem5-users] DRAM memory access latency

2014-11-06 Thread Prathap Kolakkampadath via gem5-users
gest >> checking the source code. >> >> Note that the controller is not just accounting for the static (and >> dynamic) DRAM latency, but also the static controller pipeline latency (and >> dynamic queueing latency). The controller static latency is two parameters

Re: [gem5-users] DRAM memory access latency

2014-11-06 Thread Prathap Kolakkampadath via gem5-users
The controller static latency is two parameters > that are by default also adding a few 10’s of nanoseconds. > > Let me know if you need more help breaking out the various components. > > Andreas > > From: Prathap Kolakkampadath via gem5-users > Reply-To: Prathap Kol

Re: [gem5-users] DRAM memory access latency

2014-11-04 Thread Prathap Kolakkampadath via gem5-users
MemAccLat ? >> Also when avgRdQLen is 2, i am not sure what amounts to high queueing >> latency? >> >> Regards, >> Prathap >> >> >> >> On Tue, Nov 4, 2014 at 1:38 PM, Amin Farmahini wrote: >> >>> Prathap, >>> >>>

Re: [gem5-users] DRAM memory access latency

2014-11-04 Thread Prathap Kolakkampadath via gem5-users
4, 2014 at 1:28 PM, Prathap Kolakkampadath via gem5-users < > gem5-users@gem5.org> wrote: > >> Hello Users, >> >> I am measuring DRAM worst case memory access latency(tRP+tRCD >> +tCL+tBURST) using a latency benchmark on arm_detailed(1Ghz) with 1MB >> shared L2

[gem5-users] DRAM memory access latency

2014-11-04 Thread Prathap Kolakkampadath via gem5-users
Hello Users, I am measuring DRAM worst case memory access latency(tRP+tRCD +tCL+tBURST) using a latency benchmark on arm_detailed(1Ghz) with 1MB shared L2 cache and LPDDR3 x32 DRAM. According to DRAM timing parameters, tRP = '15ns, tRCD = '15ns', tCL = '15ns', tBURST = '5ns'. Latency measured by

Re: [gem5-users] Questions on DRAM Controller model

2014-10-16 Thread Prathap Kolakkampadath via gem5-users
reply. I read your ISPASS paper and got a fair >>>>>> understanding about the architecture. >>>>>> I am trying to reproduce the results, collected from running >>>>>> synthetic benchmarks (latency and bandwidth) on real hardware, in

Re: [gem5-users] Questions on DRAM Controller model

2014-10-15 Thread Prathap Kolakkampadath via gem5-users
RAM Controller model >>>>>> >>>>>> Hello Andreas, >>>>>> >>>>>> Thanks for your reply. I read your ISPASS paper and got a fair >>>>>> understanding about the architecture. >>>>>> I am trying to reproduce th

Re: [gem5-users] Unit of avg_miss_latency

2014-10-14 Thread Prathap Kolakkampadath via gem5-users
Thanks Amin On Oct 14, 2014 8:27 PM, "Amin Farmahini" wrote: > pico second. Each tick is a pico second in gem5. > > Amin > > On Tue, Oct 14, 2014 at 7:53 PM, Prathap Kolakkampadath via gem5-users < > gem5-users@gem5.org> wrote: > >> Hi Users, >>

[gem5-users] Unit of avg_miss_latency

2014-10-14 Thread Prathap Kolakkampadath via gem5-users
Hi Users, Below is the avg miss latency for l2 captured from stats.txt. What is the unit of this? Does this mean 230ns? system.l2.ReadReq_avg_miss_latency::cpu0.data 230466.136072 # average ReadReq miss latency Thanks, Prathap __

Re: [gem5-users] Questions on DRAM Controller model

2014-10-14 Thread Prathap Kolakkampadath via gem5-users
with sequential access) >>>>> as the co-runner task. >>>>> >>>>> >>>>> On real hardware >>>>> case 1 - 0 corunner : latency of the test is 74.88ns and b/w >>>>> 854.74MB/s >>>>> case 2

Re: [gem5-users] Questions on DRAM Controller model

2014-10-13 Thread Prathap Kolakkampadath via gem5-users
ulator >>>> case 1 - 0 corunner : latency of the test is 76.08ns and b/w >>>> 802.25MB/s >>>> case 2 - 1 corunner : latency of the test is 93.69ns and b/w 651.57MB/s >>>> >>>> >>>> Case 1 where latency test run alone(0 corunne

Re: [gem5-users] Questions on DRAM Controller model

2014-10-13 Thread Prathap Kolakkampadath via gem5-users
ner), >>> the results varies a lot. >>> Do you have any thoughts about this? >>> Thanks, >>> Prathap >>> >>> On Mon, Sep 8, 2014 at 1:46 PM, Andreas Hansson >> > wrote: >>> >>>> Hi Prathap, >>>> >>&

Re: [gem5-users] Questions on DRAM Controller model

2014-10-12 Thread Prathap Kolakkampadath via gem5-users
s a C++ model, so the scheduler executes in 0 >>>time. Thus, when looking at the various requests it effectively sees all >>>the banks. >>>3. Yes and no. See above. >>> >>> Remember that this is a model. The goal is not to be representative down >&g

Re: [gem5-users] Questions on DRAM Controller model

2014-10-12 Thread Prathap Kolakkampadath via gem5-users
down >> to every last element of an RTL design. The goal is to be representative of >> a real design, and then be fast. Both of these goals are delivered upon by >> the model. >> >> I hope that explains it. IF there is anything in the results you do not >> agree with, pl

Re: [gem5-users] Tracking DRAM read/write requests

2014-10-04 Thread Prathap Kolakkampadath via gem5-users
Hi Users, Thanks Amin. You said it right. The miss rate of my benchmark was low. I have modified the benchmark so that every read request is a cache miss. After this i could see improvements and DRAM queue is getting filled. However when I print the queue size from reorderQueue(), I observe that

[gem5-users] Tracking DRAM read/write requests

2014-10-03 Thread Prathap Kolakkampadath via gem5-users
Hi Users, I am using an O3 4 cpu ARMv7 with DDR3_1600_x64. L1 I/Dcache size=32k and L2Cache size=1MB. #MSHRs' L1 = 10 and #MSHRs' L2 = 30.According to my understanding, this will enable each core to generate 10 outstanding memory requests. I am running a bandwidth test on all cpu's, which is memor

Re: [gem5-users] Query regarding DRAM controller's FR-FCFC scheduler implementation.

2014-10-01 Thread Prathap Kolakkampadath via gem5-users
ng multiple row hits." > > Thanks, > Amin > > On Wed, Oct 1, 2014 at 1:59 PM, Prathap Kolakkampadath via gem5-users < > gem5-users@gem5.org> wrote: > >> Hi Users, >> >> >> I am going through the FR-FCFS implementaion of gem5 DRAM Controller. >>

Re: [gem5-users] Query regarding DRAM controller's FR-FCFS scheduler implementation.

2014-10-01 Thread Prathap Kolakkampadath via gem5-users
On Wed, Oct 1, 2014 at 1:59 PM, Prathap Kolakkampadath wrote: > Hi Users, > > > I am going through the FR-FCFS implementaion of gem5 DRAM Controller. > > When the queue.size() is greater than 1 and memSchedPolicy == > Enums::frfcfs, the ChooseNext function calls reorderQueue. > > The reorderQueue

[gem5-users] Query regarding DRAM controller's FR-FCFC scheduler implementation.

2014-10-01 Thread Prathap Kolakkampadath via gem5-users
Hi Users, I am going through the FR-FCFS implementaion of gem5 DRAM Controller. When the queue.size() is greater than 1 and memSchedPolicy == Enums::frfcfs, the ChooseNext function calls reorderQueue. The reorderQueue function searches for row hits first in the queue and if there is a row hit

Re: [gem5-users] Questions on DRAM Controller model

2014-09-09 Thread Prathap Kolakkampadath via gem5-users
ative of > a real design, and then be fast. Both of these goals are delivered upon by > the model. > > I hope that explains it. IF there is anything in the results you do not > agree with, please do say so. > > Thanks, > > Andreas > > From: Prathap Kolakkampadat

[gem5-users] Switching CPU type from a checkpoint fails when using memory type dramsim2

2014-09-09 Thread Prathap Kolakkampadath via gem5-users
Hello Everybody, I have created a checkpoint with cpu type 'atomic' and mem type 'dramsim2. While switching to cpu type 'detailed' from this checkpoint simulation fails with below error. Switch at curTick count:1 info: Entering event queue @ 3534903961500. Starting simulation... writing vis

[gem5-users] Questions on DRAM Controller model

2014-09-08 Thread Prathap Kolakkampadath via gem5-users
Hello Everybody, I am using DDR3_1600_x64. I am trying to understand the memory controller design and have few doubts about it. 1) Do the memory controller has a separate Bank request buffer (read and write buffer) for each bank or just a global queue? 2) Is there a scheduler per bank which arb

Re: [gem5-users] Switching from Atomic CPU to Detailed CPU after Linux booted up

2014-09-03 Thread Prathap Kolakkampadath via gem5-users
s creates a checkpoint > 3) Restore from the checkpoint with the detailed CPU (specify the desired > cpu model and also "-r1" to restore from the checkpoint) > > > > > On Tue, Sep 2, 2014 at 3:20 PM, Prathap Kolakkampadath via gem5-users < > gem5-users@gem5.org>

[gem5-users] Switching from Atomic CPU to Detailed CPU after Linux booted up

2014-09-02 Thread Prathap Kolakkampadath via gem5-users
Hi Users, I am trying to run some benchmarks on ARM detailed cpu. However the simulation takes a very long time for linux to bootup and is stuck at freeing init memory and not mounting the filesystem. In case of atomic cpu, the kernel boots up to console quite fastly. I would like to know if i ca

Re: [gem5-users] How to add shared nonblocking L3 cache in gem5?

2014-08-28 Thread Prathap Kolakkampadath via gem5-users
c core? > > > On Wed, Aug 27, 2014 at 2:51 AM, Andreas Hansson > wrote: > >> Hi Prathap, >> >> You can easily create a subclass of the BaseCache and give it suitable >> parameters for an L3. This should be fairly straight forward and also easy >> to instant

Re: [gem5-users] How to add shared nonblocking L3 cache in gem5?

2014-08-28 Thread Prathap Kolakkampadath via gem5-users
suitable > parameters for an L3. This should be fairly straight forward and also easy > to instantiate in the Python scripts (e.g. fs.py) > > Andreas > > From: Prathap Kolakkampadath via gem5-users > Reply-To: Prathap Kolakkampadath , gem5 users > mailing list > D

[gem5-users] How to add shared nonblocking L3 cache in gem5?

2014-08-26 Thread Prathap Kolakkampadath via gem5-users
Hi Users, I am new to gem5 and I want to add nonblacking shared Last level cache(L3). I could see L3 cache options in Options.py with default values set. However there is no entry for L3 in Caches.py and CacheConfig.py. So extending Cache.py and CacheConfig.py would be enough to create L3 cache?

Re: [gem5-users] Integrate DRAMSim2 with gem5

2014-08-25 Thread Prathap Kolakkampadath via gem5-users
ahoo > Research Scholar > IIT Bhubaneswar > > > On Sun, Aug 24, 2014 at 11:16 PM, Prathap Kolakkampadath via gem5-users < > gem5-users@gem5.org> wrote: > >> Hi Users, >> >> Has anyone successfully integrated DRAMSim2 with gem5? If so please >>

[gem5-users] Integrate DRAMSim2 with gem5

2014-08-24 Thread Prathap Kolakkampadath via gem5-users
Hi Users, Has anyone successfully integrated DRAMSim2 with gem5? If so please point me to the patch and the version of gem5 used. Thanks, Prathap ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users