In that case whether the MSHR's would be shared between 2 L2 Caches or can have separate MSHR for each L2 cache?
Thanks. On Thu, Aug 28, 2014 at 11:52 AM, Andreas Hansson <andreas.hans...@arm.com> wrote: > Hi Prathap, > > Definitely. The gem5 memory system let’s you build any tree-topology you > like, even unbalanced (L2 for one core, and no L2 for another etc, 2 core > for one L2 and a single core for the next). Just instantiate an L2 per > core, connect it with a CoherentBus to the L1s of that core, and then use a > CoherentBus on the memory-side of the L2 to “merge” the tree into the L3 > (or use split L3’s as well). > > If you’ve got pydot installed gem5 generates a PDF/SVG showing the > system layout to visually ensure you’ve accomplished what you intended. > > Andreas > > From: Prathap Kolakkampadath <kvprat...@gmail.com> > Date: Thursday, 28 August 2014 17:47 > To: Andreas Hansson <andreas.hans...@arm.com> > Cc: gem5 users mailing list <gem5-users@gem5.org> > Subject: Re: [gem5-users] How to add shared nonblocking L3 cache in gem5? > > Thanks Andreas. I have one more question regarding cache. Is it posible > to create a system with multiple L2 caches each private to a specific core? > > > On Wed, Aug 27, 2014 at 2:51 AM, Andreas Hansson <andreas.hans...@arm.com> > wrote: > >> Hi Prathap, >> >> You can easily create a subclass of the BaseCache and give it suitable >> parameters for an L3. This should be fairly straight forward and also easy >> to instantiate in the Python scripts (e.g. fs.py) >> >> Andreas >> >> From: Prathap Kolakkampadath via gem5-users <gem5-users@gem5.org> >> Reply-To: Prathap Kolakkampadath <kvprat...@gmail.com>, gem5 users >> mailing list <gem5-users@gem5.org> >> Date: Wednesday, 27 August 2014 05:25 >> To: gem5 users mailing list <gem5-users@gem5.org> >> Subject: [gem5-users] How to add shared nonblocking L3 cache in gem5? >> >> Hi Users, >> >> >> I am new to gem5 and I want to add nonblacking shared Last level >> cache(L3). I could see L3 cache options in Options.py with default values >> set. However there is no entry for L3 in Caches.py and CacheConfig.py. >> >> So extending Cache.py and CacheConfig.py would be enough to create L3 >> cache? >> >> >> Thanks, >> Prathap >> >> >> -- IMPORTANT NOTICE: The contents of this email and any attachments are >> confidential and may also be privileged. If you are not the intended >> recipient, please notify the sender immediately and do not disclose the >> contents to any other person, use it for any purpose, or store or copy the >> information in any medium. Thank you. >> >> ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, >> Registered in England & Wales, Company No: 2557590 >> ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, >> Registered in England & Wales, Company No: 2548782 >> > > > -- IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > > ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, > Registered in England & Wales, Company No: 2557590 > ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, > Registered in England & Wales, Company No: 2548782 >
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