[gem5-users] Sorry for my inappropriate responses

everyone for my inappropriate behavior. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] documents on O3 cpu implementation?

On Sat, January 26, 2013 9:00 pm, Mitch Hayenga wrote: > Nilay, > > Stop talking down to this guy like he is someone without any > understanding. > Granted this email list gets a lot of "dumb" questions. But you jump to > conclusions too fast and are too condescen

Re: [gem5-users] documents on O3 cpu implementation?

for computer engineering / science. You should read some under-graduate textbooks on designing digital circuits and computer architecture. It seems that would be more helpful rather than trying to understand how gem5 implements an out-of-order cpu. -- Nilay ___ g

Re: [gem5-users] Last leve cache accesses

I don't > know if it indicates who made the request. > Is there a debug flag for this ? No, I don't think there is a debug flag for printing such a specific info. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.or

Re: [gem5-users] Running benchmark on FS X86 : Assertion `!delayedResponse' failed.

it hangs like forever reporting that these > instructions not implemented even though I used -mfpmath=sse > > any help with this ? > You can implement the instructions that are reported to be unimplemented. -- Nilay ___ gem5-users mailing li

Re: [gem5-users] documents on O3 cpu implementation?

certain order. The documentation on this page is probably the best you can find -- http://gem5.org/O3CPU -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] How to print current tick

ally just add a call to dump statistics before the call for execution of the benchmark. The stats file will have the tick value when the statistics were dumped. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] About statistics

ameter you changed between the two simulations? -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] A question to gem5 mounting disk image

ocol family 17 > NET: Registered protocol family 15 > Bridge firewalling registered > 802.1Q VLAN Support v1.8 Ben Greear > All bugs added by David S. Miller > VFS: Mounted root (ext2 filesystem) readonly. > Freeing unused kernel memory: 224

Re: [gem5-users] A question to gem5 mounting disk image

tes > gem5 has printed a nice error message for you. You should take a look at src/sim/system.cc, line 124. Try to figure out what went wrong. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] About statistics

mory) same or different? >> Did your simulation actually run? Because the topmost statistic listed in the file stats.txt, which is sim_seconds, denotes the time spent in the simulated system for the simulation. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] About statistics

y of the memory) same or different? -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] A question to gem5 mounting disk image

but still didn't work. > > > > I modified FSConfig.py and Syspath.py file repectively, changing the > default disk image configuration, but I didn't find the item that > indicates my mounting point. Can anyone help? Thanks! > What's the error that you get? -- N

Re: [gem5-users] Access to Host Machine from the Simulated OS

age before without having > to reboot the simulated OS? > You can access the host machine (it is done for reading the rcS script). As per my understanding, it is possible to replicate that facility to read a binary file and execute it. I don't think the vanilla gem5

Re: [gem5-users] gem5 cache hierarchy reformation

, 2013 7:41 am, preethi pd wrote: > Hi Nilay, > > > Thanks for ur mail. > > No my configuration will be > > 1. Private L1 cashes with shared L2 in bus based clusters with a > write-through read policy. Buses are not supported. But you can build a cluster using a switch. Wr

Re: [gem5-users] gem5 cache hierarchy reformation

ion? > 2) L2 cache with directory based coherency module structure variation as > per my internal use. > > -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] How do I print out the binary content of cache lines

nsmitted to the > interconnect. > Try looking at the files in src/mem/cache or src/mem/ruby/system directories. The file names are pretty informative. With some code exploration, I think you will be able to find the answer to your question. -- Nilay ___ ge

Re: [gem5-users] Error building gem5: "compiler: None"

16 CXX='/usr/bin/g++' build/X86/gem5.debug. Read more about the build system here -- http://gem5.org/Build_System -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] prefetcher configuration has been changed

pf.py", line 31, in > > class Prefetcher(BasePrefetcher): > File "/home/mahmood/gem5/src/python/m5/SimObject.py", line 137, in > __new__ > assert name not in allClasses, "SimObject %s already present" % name > AssertionError: SimObject Prefetcher

Re: [gem5-users] Again... "Tried to write unmapped address"

ve your problem -- http://reviews.gem5.org/r/1658/ -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Again... "Tried to write unmapped address"

hed the output and > config.ini and the config file (which is the same as above). > > > Also, please note that although I used a unique value for fast > forwarding, the reported switch cpu tick is different in two revisions > which is strange for me. > You did not mention the ve

Re: [gem5-users] Again... "Tried to write unmapped address"

original configuration is same as the one that you are using now. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Does gem5 support multi-cores in the host-machine? I don't mean the emulated structure!

On Fri, January 18, 2013 5:20 pm, Alshamlan, Mohammad wrote: > so by parallelizing gem5, it wouldn't sacrifice its accurate and precise > timing for the emulated system. I see, thanks. > Depends on how you parallelize it. -- Nilay

Re: [gem5-users] Does gem5 support multi-cores in the host-machine? I don't mean the emulated structure!

On Fri, January 18, 2013 5:09 pm, Alshamlan, Mohammad wrote: > Hi Nilay, > > Okay, let me understand this, gem5 runs as a single process with just one > thread of execution because of accuracy and precision reasons! Or because > the multi-thread in the host hasn't been devel

Re: [gem5-users] Does gem5 support multi-cores in the host-machine? I don't mean the emulated structure!

7;s in the > host-machine? Thanks in advance. > You cannot. gem5 is runs as a single process with just one thread of execution. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Gem5 and trace-driven simulation

Andreas, you should really write a page on the traffic generator and its capabilities. -- Nilay On Wed, 16 Jan 2013, Andreas Hansson wrote: Hi Victor, The TrafficGen module (in src/cpu/testers) supports trace replay. The trace format is the same as what the gem5 CommMonitor produces, but

Re: [gem5-users] Trouble with Running X86 with o3cpu

u know the problem has not been solved, can you spend some time in figuring out why the problem might be occurring? I am surprised that you believe some one can look at the above 5 line abort message and tell you where and what the problem is. -- Nilay __

Re: [gem5-users] Ruby L2 Cache Latency

e were to reply, how are you going to confirm that the answer is correct? Or if no one responds, how will you figure out what the answer is? -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Sincere Query of Tracking Benchmarks in FS

Here is the link -- http://www.gem5.org/M5ops -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] [gem5-dev] Alpha trace files

registers in the trace whenever the processor is executing PAL code. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Running Multi-Threaded Benchmarks on Multi-Core systems

This would help you understanding what went wrong when you issued the above command. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] How I run the benchmark?

On Sun, 13 Jan 2013, Abu Saad wrote: *Hi all How I run the benchmark on gem5?* You should read the documentation available on gem5.org. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Segmentation fault when restoring checkpoint in X86 SE

at the end of the simulation. You need to pull in the changeset. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Segmentation fault when restoring checkpoint in X86 SE

On Thu, 10 Jan 2013, Nilay Vaish wrote: Your trace was not of much help since it is not immediately clear as to what pointer is being dereferenced incorrectly (one of the major causes of segmentation faults). But I was able to reproduce the problem. The following variable is invalid

Re: [gem5-users] Running benchmark on FS X86 : Assertion `!delayedResponse' failed.

claiming is incorrect, it seems not a single translation would happen. Why don't you test your theory to check if that is the case? -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Segmentation fault when restoring checkpoint in X86 SE

the beginning. It appears to be an initialization issue to me, but I was not able to figure out the exact cause. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Running benchmark on FS X86 : Assertion `!delayedResponse' failed.

What all did you try to solve this issue? Your initial reasoning for the problem was certainly incorrect. -- Nilay On Fri, 11 Jan 2013, Mostafa Mahmoud Hassan wrote: Any guesses with this guys ? Regards -- why do you think

Re: [gem5-users] TLB miss occurs when it has matched entry

On Thu, January 10, 2013 11:53 am, Jinchun Kim wrote: > Thanks for the head up Nilay. > I'm not sure how to check if it is valid or not, so I just printed out all > tlb entry information and compared it. > > 4949688231000: system.cpu.dtb: tlb2[39] entry : VPN : 0x7fab3f32c000,

Re: [gem5-users] Segmentation fault when restoring checkpoint in X86 SE

ot the application. It should be straight forward to figure out where the segmentation fault occurred using gdb. Post the function call stack. It should be possible to figure out the cause that. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] 答复: Two level directory ccNuma

achievable or not. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] [X86-O3] Instruction class not properly defined

fied. > > PS : In the wiki, there is a definition of the microops used in the X86 > implementation, but there is none (that I found) for SSE. Does it exist > or do I have to go fish in the .isa files? > There are SSE instructions that have

Re: [gem5-users] Running Multi-Threaded Benchmarks on Multi-Core systems

benchmark or the OS) in your simulation cannot have the same sequence of five or more instructions. -- Nilay On Wed, January 9, 2013 4:32 am, Bahar Asgari wrote: > Hello > I've faced a problem during running PARSEC Multi-threaded benchmarks on > gem5 in "fs" mode > First I&#

Re: [gem5-users] want to know what are the meaning

bout debug-flags here -- http://www.gem5.org/Trace_Based_Debugging. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Two level directory ccNuma

what your system looks like, I might be able to tell you how to configure it. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] x86 FS mode with SMT

rking with x86 FS? I do expect checkpoints to work correctly, especially after the recent work carried out by some of the developers at ARM. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Regarding changeset 9457: util: add m5_fail op

This changeset adds code to configs/common/Simulation.py which tries to access a variable before it has been assigned any value. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] X86 FS + ruby command line options are ignored

"0" (*eax), "2" (*ecx)); } but it seems that the asm code is calling cpuid again ! cpuid is an x86 instruction. Read about the info returned by cpuid and figure out how gem5 implements this instruction. That should provide answer to your original question. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Regarding changeset 9396

n you verify that: http://reviews.gem5.org/r/1615/ resolves the issue? I'll do it some time later today. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Regarding changeset 9396

On Tue, 8 Jan 2013, Andreas Hansson wrote: Hi Nilay, I am not sure I follow your comment. pkg-config is used for protobuf, but not for anything else at this point. I cannot reproduce the error on my side as my pkg-config knows of protobuf and handles it correctly. The tests in the scons script

Re: [gem5-users] X86 FS + ruby command line options are ignored

during boot time. -- Nilay I guess the info shown on the terminal is misleading, I checked the "config.ini" file in the results directory and found this : [system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 is_icache=false latency=3 replacement_policy=PSEUDO_LRU size=131072 start

Re: [gem5-users] TLB miss occurs when it has matched entry

On Mon, 7 Jan 2013, Jinchun Kim wrote: It's X86 FS and classic model. Jinchun Kim On Jan 7, 2013, at 4:17 PM, Nilay Vaish wrote: On Mon, 7 Jan 2013, Jinchun Kim wrote: I was printing out TLB entries whenever virtual address hit or miss on TLB. And I found that TLB miss occurs even t

Re: [gem5-users] Regarding changeset 9396

On Mon, 7 Jan 2013, Ali Saidi wrote: Hi Nilay, Do you have protoc installed, but pkg-config doesn't know about it? Yes, but it should not matter. I would expect that protoc and the associated libraries are detected like gcc. -- Nilay ___

[gem5-users] Regarding changeset 9396

-config search path. Perhaps you should add the directory containing `protobuf.pc' to the PKG_CONFIG_PATH environment variable No package 'protobuf' found OSError: 'pkg-config --cflags --libs-only-L protobuf' exited 1: File "/scratch/nilay/GEM5/gem5/SConstruct",

Re: [gem5-users] TLB miss occurs when it has matched entry

x27;t understand why gem5 can't find proper translation when it is already in TLB and put same translation again. Which architecture? -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Gem5 compiling error

ot;-j 2" (or not using -j at all). If you're running into problems with 4GB of RAM, make sure you're not using a -j argument larger than 2, and that you don't have any other large memory-consuming processes running. Steve, are you talking about gem5.opt? -- Nilay _

Re: [gem5-users] X86 FS + ruby command line options are ignored

the kernel displays cache info during boot time. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] X86 FS + ruby command line options are ignored

all the info in /sys is generated when the system is booted. It might be that the code in the kernel that generates info for /sys is never executed. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] What to do before instantiating gem5?

-- I copied my script mostly from Hipeac conference slides in tutorials; You might want to try out gem5 with scripts from configs/examples/ directory. In particular, check whether se.py works for you or not. You can read the documentation on gem5.org on how to use these scripts. -- Ni

Re: [gem5-users] X86 FS + ruby command line options are ignored

, type="string", default="64kB") parser.add_option("--l1i_size", type="string", default="32kB") parser.add_option("--l2_size", type="string", default="2MB") which totally different from my chosen values for these options. can any one

Re: [gem5-users] Question about TBE of cache protocol

Data: qq_sendWBDataFromTBE; s_deallocateTBE; l_popForwardQueue; I'm strange is this possible in real world? Having TBEs seems one of the possible ways to implement a coherence protocol. I don't think they are necessary, but they don't seem implausi

Re: [gem5-users] FW: Help with more than 4 CPUs FS

On Mon, 31 Dec 2012, Nilay Vaish wrote: On Mon, 31 Dec 2012, Mostafa Mahmoud Hassan wrote: Hi Nilay 1) I tried increasing the memory in FSConfig to 2047MB 2) I tried to use timing simple CPU instead of detailed 3) I tried to decrease the number of objects (number of L2 Cache banks

Re: [gem5-users] FW: Help with more than 4 CPUs FS

On Mon, 31 Dec 2012, Mostafa Mahmoud Hassan wrote: Hi Nilay 1) I tried increasing the memory in FSConfig to 2047MB 2) I tried to use timing simple CPU instead of detailed 3) I tried to decrease the number of objects (number of L2 Cache banks, number of directories) hoping that the

Re: [gem5-users] Help with more than 4 CPUs FS

hours) > So what all things did you try out to solve this problem? -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] How to know if benchmark is running or not

d. Since you are running an operating system on the simulated machine, it is the operating system which will figure out if there is some problem with the commands in the rCS file. Take a look at the terminal for the simulated system, I would expect it to show that th

Re: [gem5-users] about simulation statistics

t > be proof enough. > Why do you think the statistics should be similar? How close are the simulated and native systems in the terms of gem5's configuration? -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] about SLICC compiler

other tools? > No such method is available in gem5, but it should be possible to modify some SConscript and disable SLICC. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Gem5 compiling error

ons: building terminated because of errors. gem5.opt for x86 architecture requires a lot of memory while compiling. You can either compile gem5.opt on a machine that has more RAM, or compile gem5.fast / gem5.debug. -- Nilay ___ gem5-users mailing l

Re: [gem5-users] x86 O3 TLB

On Fri, 21 Dec 2012, Xin Tong wrote: Hi Does gem5 implement a TLB for x86 O3 processor ? Yes. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] gem5 port error

any trouble or not. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] gem5 port error

On Thu, 20 Dec 2012, Jordan Fix wrote: Not sure if you mean the physical memory of the simulator or the machines they're running on. The simulator is running with 512Mb. The machine which works has 12Gb, and the machine which doesn't has 8Gb. On Dec 20, 2012, at 9:25 PM, Nilay V

Re: [gem5-users] gem5 port error

the size of the physical memory? -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Accessing a device

am not quite confident on how the device driver works with the device itself. I dobut directly specifying the address of the device will work. I think the processor will consider it to be a regular virtual address and try to map it some physical address, which should fail and

Re: [gem5-users] [O3] Early D-Cache access on store execution

hem. This means that some other core may observe the stores being carried out in the opposite order, violating TSO. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] How to call some function when execute 'dumpresetstats'

don't think dumping and resetting ruby statistics has been done by 'dumpreststats'. On 12/16/2012 11:33 PM, Nilay Vaish wrote: On Sun, 16 Dec 2012, zhengchl wrote: Hi, I want to call function 'Profiler::printStats' of Ruby when 'dumpresetstats' is executed. So I tra

Re: [gem5-users] simulation methodology

.g., if the dump order is c1->c2->c0->c3, then we get stats related to c0 in the 1st dump and that to c2 in the 2nd dump and so on. Here we must note that the stats dump order mirrors the order in which every program finishes N3 instructions. It is not too hard to print when

Re: [gem5-users] How to call some function when execute 'dumpresetstats'

On Sun, 16 Dec 2012, zhengchl wrote: Hi, I want to call function 'Profiler::printStats' of Ruby when 'dumpresetstats' is executed. So I track the the call stack of dumpresetstats. I guess you are bent on doing something that alrea

Re: [gem5-users] Could not load console file

On Sun, 16 Dec 2012, pmo...@masonlive.gmu.edu wrote: Thank you Nilay. I don't know where to change the parameters so it will look for console in the path I have put it in and not the default. I spent all day looking in different files and change parameters and I still get the same erro

Re: [gem5-users] how to connect dummy device

Andreas, can you add a page on the traffic generator to the Wiki? Thanks Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Could not load console file

be enough to get you started on why this problem is occurring. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] does gem5 run on Solaris-Sparc 64 bit?

On Thu, 13 Dec 2012, sarde...@uci.edu wrote: Hi Nilay, Yes, I had to make two changes to make it compile. 1. Solaris does not recognize std::isnan() function. So I had to put my own implementation. This was a solution posted online > https://gist.github.com/870503 -namespace std -{ -

Re: [gem5-users] How to get ruby cache statistics of a interested region

t' is about the entire simulation process and I only want the information of interested region. So, how to get ruby statistics of a interested region? As I understand, the current version of gem5 dumps and resets statistics for Ruby, whenever dumpresetstats is

Re: [gem5-users] simulation methodology

osing. Why is it essential that each core has executed exactly N3 instructions? Is this experiment realistic? -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] does gem5 run on Solaris-Sparc 64 bit?

might want to go through those changes again to make sure you did not do any thing incorrect. 2. Since you have a debug binary, you should be able to use gdb's equivalent on Solaris to figure out why the program failed. -- Nilay ___ gem5-use

Re: [gem5-users] simulation methodology

, when all the programs have executed at least N2 instructions, reset the statistics and start the detailed simulation. If you look in to how the options -F and -W are used in the file configs/common/Simulation.py, you should be able to make it work for multiple CPU system as well.

Re: [gem5-users] Splash2 error: cannot execute binary file

On Wed, 12 Dec 2012, 刘宇航 wrote: Hi all, Under FS mode while using Ruby, I run the splash benchmark using the pre-compiled v1-spalsh-alpha.tgz from http://gem5.org/Download, but encounter the following error: modprobe: FATAL: Could not load /lib/modules/2.6.27.6-dirty/modules.dep: No such fi

Re: [gem5-users] Mismatching about L2 Configuration for ARM FS

le to nail which of the hypothesis you suggested is correct. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] SLICC L1 Cache

mpile with these changes. Am I doing something wrong? The SLICC compiler yells at me with saying, there are errors in Builder.py and a bunch of other PY files. What's that comma doing after M_I? -- Nilay ___ gem5-users mailing list gem5-users@gem

Re: [gem5-users] Question about L2 misses in ruby.stats

e. I don't understand why ruby collect L2 cache access and miss in this way.. Is there any way to calculate ACTUAL L2 cache access and misses? Which protocol are you using? -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/m

Re: [gem5-users] Re-ordering buffers in Ruby

On Fri, 7 Dec 2012, Anouk wrote: Hi Nilay, Thanks for your answer. I am changing my response. Depending on the protocol, there are operations that are carried out which might be termed as re-ordering. For example, a controller may block all messages while it is waiting for a particular

Re: [gem5-users] Re-ordering buffers in Ruby

present in Ruby and if so, could you please give some pointers as to where that would be? Ruby does not maintain any ordering information about the packets. Depending on the parameter values, it can force links in the network to transmit packets in a FIFO order. -- Nilay

Re: [gem5-users] Query on Generating Trace File for Last Level Caches

changes, this means that there is no L3 cache in the system. Take a look at the file configs/common/CacheConfig.py. It shows how to add the L2 cache. Adding an L3 cache should be similar. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http

Re: [gem5-users] Query on Generating Trace File for Last Level Caches

--l1i_size=32kB --l1d_assoc=8 --l1i_assoc=4 --l2cache --l2_size=256kB --l2_assoc=8 --l3_size=8192kB --l3_assoc=16 -c v1-splash-alpha/splash2/codes/kernels/radix/RADIX Can you confirm that an L3 cache is present in the simulated system? -- Nilay ___ gem5-users

Re: [gem5-users] Help need with cache state transition

id transition, this means that the controller does not know what to do for the given (state,event) pair. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Ruby model Cache related query

command line arguments. The very first assertion in the CacheMemory->init() fails and the program terminates. This assertion condition is as follows, assert(m_cache_num_sets>1); You will get your answer if you run gem5 without the changes that you have made. --

Re: [gem5-users] No ruby.stats output

/gem5.debug configs/example/se.py -c tests/test-progs/hello/bin/mips/linux/hello The program successfully run and generate 3 file config.ini, config.json, stats.txt Add the option --ruby in that command line to make use of the ruby memory system. -- Nilay

Re: [gem5-users] Interactions between memory system and instructions

ferent parts of Ruby. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] where is LLSC flag set for a request in ALPHA architecture

On Sun, 2 Dec 2012, Anusha wrote: I am not to find the place where this LLSC flag is actually set. (I wasn't able to find any code that used SetFlags(LLSC)). Am I missing something here? Of course! You are missing the power of grep. --

Re: [gem5-users] Cache tag entry query

acheMemory::allocate(). You should be able to figure out how m_cache and m_tag_index are populated. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Full system benchmarks exit after execption

fixed -n 4 --num-l2caches=4 --num-dirs=4 --l1d_size=512B --l1d_assoc=2 --l1i_size=512B --l1i_assoc=2 --l2_size=4kB --l2_assoc=2 Does anyone have any idea on how to solve this exception? Thank you so much Why don't you try to figure out where the class ConfigFile is being

Re: [gem5-users] a question about Ruby and cache coherence protocols

On Sat, 1 Dec 2012, leonardo wrote: Hello everyone Is there any chance that I could use Ruby without any cache coherence protocols? What should i do? Thanks. Does not seem possible to me. You can use the classic memory system, if it serves your purpose. -- Nilay

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