I can see the statistic "Miss Latency" declared in base.hh, updated in
cache.cc. I can also see it in the stats.txt file in m5out directory.
I cannot see any such thing for "hit latency". It is also declared, but I
cannot find it updated anywhere, nor reported in stats.txt.
What am I missing or
Hello.
Suppose I have 4 addresses going to cache from cpu, A1, A2, A3 and A4. All are
read requests.
Assume, my L1 cache is blocking.
Now, load store unit will first sent A1.
if it is a miss, the L1 will send it to L2. If it is a L2 hit, it will send the
data back to L1, then L1 will send it back
Hello.
In tags/indexingPolicy/base.cc there is an extractTag function.
In base.hh the prototype is:
virtual Addr extractTag(const Addr addr) const;
In base.cc, the definition is:
Addr
BaseIndexingPolicy::extractTag(const Addr addr) const
{
return (addr >> tagShift);
}
Whether it is set associ
Hello. I have some questions regarding writes.
In base.cc, updateBlockData() method calls writeDataToBlock() of PacketPtr
class.
Following are my questions:
1.
Inside writedatatoblock(), there is : writeData(blk_data + getOffset(blkSize));
here, blk_data is a 8 bit value (uint8_t). But in the
Hello. I was going over the files for sector tags and trying to figure out how
they are supposed to be working.
What I can understand is, compared with a set associative cache, the "sets" are
sets of "sectors" instead of "ways", each sector having one or more subsectors
(which are the actual cac
Hello.
There is a FALRU() class in src/mem/cache/tags.
Now, in the config/common/CacheConfig.py, if I instantiate l1 Data cache, and
then do:
dcache.tags=FALRU();
Will this work ?
Or do I need to, calculate by hand the number of cacheline in my cahce , based
on cacheline size and cache size and
Hello.
Is there a way, to change cacheline size for different level of cache ?
Example: L1 cacheline size is 64 byte and L2 is 128 bytes ?
If there is not a direct way (changing some parameter from python), what will
be the issues with building this ?
Things I know:
1. fetchbuffer size has to be
nks or open attachments unless you are sure the content is safe.
On 2/6/2024 11:13 AM, Nazmus Sakib via gem5-users wrote:
> I think gem5 has this SplitDataRequest() method that breaks the request if it
> would need more than one cacheline.
> In fact, the page fault is occurring before
du. Learn why this is
> important at
> https://aka.ms/LearnAboutSenderIdentification
> <https://aka.ms/LearnAboutSenderIdentification> ]
>
> WARNING This email originated external to the NMSU email system. Do not click
> on links or open attachments unless you
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RNING This email originated external to the NMSU email system. Do not click
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On 2/5/2024 10:41 AM, Nazmus Sakib via gem5-users wrote:
> Hello.
> I was trying to find how the virtual (logical) addresses are calculated and
Hello.
I was trying to find how the virtual (logical) addresses are calculated and
passed on to cpu.
In the load/store queee, after a request object is created, then the
corresponding instruction is assigned a effective address from this request
object, something like inst->effaddr=req->getVirt(
pecifying the VL. Then it should be VL agnostic code I presume.
Anyway, I also recommend you use configs/example/arm/starter_se.py as se.py is
per se deprecated
Kind Regards
Giacomo
[1]: https://github.com/gem5/gem5/blob/stable/src/arch/arm/ArmISA.py#L179
From: Nazmus Sakib
gnostic code I presume.
Anyway, I also recommend you use configs/example/arm/starter_se.py as se.py is
per se deprecated
Kind Regards
Giacomo
[1]: https://github.com/gem5/gem5/blob/stable/src/arch/arm/ArmISA.py#L179
From: Nazmus Sakib via gem5-users
<mailto:gem5-users@gem5.org&g
it should be VL agnostic code I presume.
Anyway, I also recommend you use configs/example/arm/starter_se.py as se.py is
per se deprecated
Kind Regards
Giacomo
[1]: https://github.com/gem5/gem5/blob/stable/src/arch/arm/ArmISA.py#L179
From: Nazmus Sakib via gem5-users
<mailt
be to compile
without specifying the VL. Then it should be VL agnostic code I presume.
Anyway, I also recommend you use configs/example/arm/starter_se.py as se.py is
per se deprecated
Kind Regards
Giacomo
[1]: https://github.com/gem5/gem5/blob/stable/src/arch/arm/ArmISA.py#L179
use configs/example/arm/starter_se.py as se.py is
per se deprecated
Kind Regards
Giacomo
[1]: https://github.com/gem5/gem5/blob/stable/src/arch/arm/ArmISA.py#L179
From: Nazmus Sakib via gem5-users
Date: Thursday, 11 January 2024 at 17:54
To: gem5-users@gem5.org
Cc: Jason Lowe-Power , N
Hello.
I am trying to run a simple program with SVE instructions on gem5. However, the
output with debug flag ExecALL suggests there is a issue with the decoder.
Here is the test code:
#define STREAM_ARRAY_SIZE 16
void main()
{
for (int j=0; j___
gem5-us
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