Re: [gem5-users] Error in the process of running SPEC CPU2006 Benchmarks in the gem5 Simulator

Hi, As far as I remember, not all spec benchmarks run in the SE mode since it is probable that there exist unimplemented instructions. You can try other things such as bzip2, libquantum, ... Another less useful trick is to skip that instruction. However, if that instruction repeats so many times in

Re: [gem5-users] add parameter in params

r: > > system.ruby.network.netifs000.num_vcs without default or user set value > > On Tue, Jul 11, 2017 at 7:37 PM, Mahmood Naderan > wrote: > >> Hi, >> You have to edit the .py file in the src/ and then recompile. For >> example, have a look at src/mem/c

Re: [gem5-users] add parameter in params

Hi, You have to edit the .py file in the src/ and then recompile. For example, have a look at src/mem/cache/BaseCache.py and add your *cache* related params there and the recompile. The same can be applied to other components. Regards, Mahmood On Tue, Jul 11, 2017 at 7:31 PM, raziye deylamsaleh

Re: [gem5-users] SimPoint with gem5

Hi, Have you read http://gem5.org/Simpoints ? Regards, Mahmood On Wed, Jul 5, 2017 at 4:00 PM, Mukherjee, Somnath wrote: > Friends, > > A rather short message – wanted to know if anyone has used SimPoint with > gem5? J > > https://www.spec.org/cpu2006/research/simpoint.html > > > > If yes, ca

Re: [gem5-users] Error using runspec in SPEC2006 Benchmarks

Hi, Although it is not related to gem5, i recommecd you to directly go to the src folder of each benchmark and build that. Regards, Mahmood On 2 Feb 2017 22:57, "Muzamil Rafique" wrote: Hi All, I am trying to use runspec in an effort to compile and run SPEC2006 benchmarks and getting following

Re: [gem5-users] IDE For Gem5

​Hi, What do you mean by Gem5 itself? it is c++ code which you can debug it like other codes. Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Error on gem5.debug but no error on gem5.fast

orget all about ICS and instead > follow the instructions here: http://www.gem5.org/Android_KitKat and > here: http://www.gem5.org/WA-gem5. > > That enables you to run a wide range of workloads, using Workload > Automation on Android KitKat. > > Andreas > > From: gem5-users

[gem5-users] Error on gem5.debug but no error on gem5.fast

Hi, If I run bbench with gem5.debug, I immediately get an error in the code however, gem5.fast doesn't fail at that point. In fact it will fail after so many ticks. A bit strange... Any idea on that? I haven't modified the code yet. gem5.debug warn: DTB file specified, but no device tree suppor

Re: [gem5-users] Yet another question on BBench

OK I think I got what you said. However, I have to say that after about two hours, the simulation aborted with a panic related to VNC. I have to say I didn't attach any vncviewer since the job was running in the background yesterday night. Have you seen that before? Global frequency set at 100

[gem5-users] Yet another question on BBench

Hi, For the BBench, how can I be sure that the android is booted up in order to create a checkpoint? Also, how does it work? I mean does it automatically run the benchmark after the boot? Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org

[gem5-users] problem attaching vncviewer

Hi, As I run the bbench, the simulation window shows nothing. On another terminal running vncviewer, I get this error: ​mahmood@orca:~$ vncviewer 127.0.0.1:5900 Connected to RFB server, using protocol version 3.8 No authentication needed Authentication successful Desktop name "M5" VNC server defau

Re: [gem5-users] where to obtain 'vmlinux.aarch32.ll_20131205.0-gem5'?

Thanks. Found it... Regards, Mahmood On Thu, Dec 24, 2015 at 7:35 PM, Paul Rosenfeld (prosenfeld) < prosenf...@micron.com> wrote: > It should be in the ARM full system files: > http://www.gem5.org/dist/current/arm/aarch-system-2014-10.tar.xz > > > > tar --list -f aarch-system-2014-10.tar | gre

[gem5-users] where to obtain 'vmlinux.aarch32.ll_20131205.0-gem5'?

Hi, After some years, now getting back to gem5 for a test! I followed the instructions on how to run bbench, however got an error that relates to a missing file What is 'vmlinux.aarch32.ll_20131205.0-gem5' and where can I obtain that? seems that a step is missing in the manual. mahmood@orca:g

Re: [gem5-users] List of SPEC 2000 runnable benchmarks on gem5

The instructions are available at http://www.m5sim.org/SPEC2000_benchmarks On 3/10/15, Vanchinathan Venkataramani wrote: > Hi Andreas > > I can find the list of SPEC2006 benchmarks that can successfully run on > gem5 from the following link: > > http://www.m5sim.org/SPEC_CPU2006_benchmarks > > I

[gem5-users] mshr miss rate

Hi What does "mshr miss rate" mean? Let's say MSHR contains [A B C D] and these are the misses waiting for service. Now assume, cpu requests B. This is called MSHR hit. If cpu requests E, then that is called MHSR miss. How MSHR_miss_rate is then calculated. Is that 1/(1+1)? Shouldn't we consider n

Re: [gem5-users] Why CPI is so big

>I get the CPI by dividing sim_insts(m5out/stats.txt) >from sim_ticks and the result is 9411 CPI has a dedicated stat name. Check that. >what are the default configs for cacheline size See Options.py On 4/26/14, luming wrote: > Dear gem5 users, > > I'm new to gem5 and I ran SPEC2006 to get some

Re: [gem5-users] Prefetcher / Cache Address

If there is a way to view the data of a particular address prior to its actual request, then what does prefetching mean here? With prefetching, you generate an address and issue later to bring the data. On 4/19/14, anonymous wrote: > Fernando Endo gmail.com> writes: > >> >> >> Hello, >> I'm no

[gem5-users] cache stats

Hi What is the logic behind the definition of cache stats? For each stat, a loop is defined that assigns a subname it. -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] gem5 cache latency, impact on performance

ut execution time > value (sim_seconds) in stat file does not show a significant difference. > Alinti Mahmood Naderan > >> Sanem, >> maybe you put sleep() somewhere in the code that never executes! Can >> you confirm that by breakpoints? >> >> On 4/4/14,

Re: [gem5-users] modeling L3 last level cache in gem5

Prateek, Don't know what is config.dot.py but with config.dot.pdf you can easily verify the connections. On 4/4/14, Prateek Gupta wrote: > Hello Andreas, > > > Thanks for your reply. > Do I need to extend fs.py or se.py? I have tried making changes in > CacheConfig.py, Caches.py and > Options.py

Re: [gem5-users] gem5 cache latency, impact on performance

Sanem, maybe you put sleep() somewhere in the code that never executes! Can you confirm that by breakpoints? On 4/4/14, Sanem Arslan wrote: > Hi all, > > I am using classic memory system and I have added several codes to > the "cache_impl.hh" and "blk.hh" files. However I cannot see the > perfor

Re: [gem5-users] Question about IPC in the O3 CPU

Hi, That depends on the definition of idle cycle. Some say that idle cycles don't include cache misses because there exists some instructions in the pipeline. With such definition, idle cycles are related to thread stalls due to I/O, network, ... You have to check how idle cycles is incremented in

Re: [gem5-users] Syscall clock_gettime (#228) implemented

>fatal: syscall clock_gettime (#228) unimplemented Regrding the gettime call, if it is used to report the progress, then you can safely ignore that. Otherwise, you have to implement that. To ignore that you have to comment some lines in code! grep for the syscall and you will find that. -- Regar

Re: [gem5-users] mmap error when I increase mem-size

Anju, First you have to find is it a system related problem or gem5 bug. What is your OS? G++? GLIBC? -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] config.dot.pdf file

Thanks Andreas, I worked with se.py on one system and fs.py on another. -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] config.dot.pdf file

Hi It seems that in the full system simulation, the *.dot.pdf is not created. Can someone confirm tht? -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Parsec checkpointing at ROI for X86

Hi, Has anyone been able to take a checkpoint at the beginning of ROI for PARSEC workloads on a X86 disk image? I used the hook binaries but they ignore the hooks. -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-

Re: [gem5-users] Finding cache type in cache_impl.hh

> Original message ---- > From: Mahmood Naderan > Date: > To: gem5 users mailing list > Subject: [gem5-users] Finding cache type in cache_impl.hh > > Hi, > Since cache_impl.hh is used for all cache levels and types, how is it > possible to check whether it is

[gem5-users] Finding cache type in cache_impl.hh

Hi, Since cache_impl.hh is used for all cache levels and types, how is it possible to check whether it is used for d-cache or something else? IsTopLevel is useful for L1/L2 but what about i-cache, d-cache and page table walker? I can not find any identifier for that. -- Regards, Mahmood

Re: [gem5-users] Running SPECCPU2006 benchmarks in X86 SE mode

Add this line to Mybench.py from m5.objects import LiveProcess -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Maxticks option

Hi I have set -F 2,000,000,000 and -m 4,000,000,000,000 to simulate an eight core processor. However the final tick is not the same as what I specified Exiting @ tick 2291079562000 because target called exit() Do I need to specify something else? -- Regards, Mahmood ___

Re: [gem5-users] instruction cache miss rate result for parsec benchmark

Hi You can try other workloads or reduce the i-cache size (8KB) to verify if it working properly. On 2/28/14, Fateme Movafagh wrote: > hi all, > I am running parsec on gem5 x86 full system with --caches --cachel2 option > . > in the stat.txt file , the result of total Icache miss rate is very sma

Re: [gem5-users] Question about McPAT

Is your i-cache bigger than d-cache (in terms of KB and not mm2)? On 2/20/14, Mahshid Sedghi wrote: > Hi, > > I was wondering if anyone have done area estimation for L1 caches using > McPAT. For some reason, L1 dcache or icache is the same for > -- Regards, Mahmood

[gem5-users] cache latency unit

Hi, It seems that the latency unit has been changed from Tick (ns) to Cycle. Is that correct? For example I see class L1Cache(BaseCache): size= '32kB' assoc = 4 hit_latency = 2 response_latency = 2 is_top_level = True Using CACTI, at 45nm process technology and 2.5GHz cpu freq

[gem5-users] error on 'cpu_voltage_domain'

Hi While porting an old simulation script, I added these lines (the same as se.py) system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, voltage_domain =

[gem5-users] Three level coherency

Hi As far as I remember, there wan't any three level cache coherency in old versions. Is there any news about that? -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Splash-2 with m5threads "panic address not mapped error"

dress map. In SE > mode, without an OS present I'm not sure what it means other than all > threads/cores having a global view of memory. Shouldn't be causing my > issue. > > I'll try using Physical Memory as well. Thanks. > > > On 19 February 2014 14:18, Mahmoo

Re: [gem5-users] Splash-2 with m5threads "panic address not mapped error"

me other custom >> object code that shouldn't be called when running under Gem5 at all. This >> is evidenced by the fact that I can also run the same executable natively >> and confirm that it finishes. (I also did a Valgrind Memcheck just to make >> sure.) >>

Re: [gem5-users] Splash-2 with m5threads "panic address not mapped error"

Hi Have you modified the code in a way to create new addresses? You should note that the unmapped address is in the range of 4GB< < 8GB. If you increase the memory to 8GB, that specific address will be resolved but you may see another error for addresses larger than 8GB!! Hope that helps On 2/18

Re: [gem5-users] IPC

You can write a script to sum all committed instructions, sum(commit0, ..., commitN), and then divide that by the number of cycles -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Memory contention: Odd results

Hi >- work: which accesses memory very frequently and each > access produces a L1 and L2 miss Are you sure about that? Can you confirm that the hit stats are zero? -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi

Re: [gem5-users] DRAM prefetcher

>The pre-fetcher for L2, does it fetch from DRAM and place the data in L2 >(assuming L2 is the last level cache)? Or is it fetching from L2 and placing >the data in L1? Hi, The easiest way is to turn on the debug messages "DPRINTF" and track one prefetch request that has been issued. I am not sure

[gem5-users] Regarding ipc_total

Hi, Looking in to code cpu.cc, I see ipc .name(name() + ".ipc") .desc("IPC: Instructions Per Cycle") .precision(6); ipc = committedInsts / numCycles; totalIpc .name(name() + ".ipc_total") .desc("IPC: Total IPC of All Threads") .precisio

Re: [gem5-users] regarding mcpat

ance > > > > 2013/11/20 Amin Farmahini > >> This might give you some idea. >> https://www.cl.cam.ac.uk/~acr31/sicsa/mcpat-template.xml >> >> Amin >> >> >> On Wed, Nov 20, 2013 at 8:58 AM, Mahmood Naderan >> wrote: >> >>> Hi,

[gem5-users] regarding mcpat

Hi, While porting stats from gem5 to mcpat, I could not find the counterpart of the following stats. 1- Shall we use the same L1D stats for L1Directory? For example, are these equal 2- The same question regarding L2 and L2Directory 3- -- Regards, Mahmood ___

[gem5-users] blocking causes

Hi, I see some stats regarding block causes. system.l2.blocked_cycles::no_mshrs 9584945079 # number of cycles access was blocked system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2.blocked::no_mshrs 1765905 # number of cycles

[gem5-users] Shall we solve "unable to find destination addr" once for all ?!

Hi I think I found why randomly one receives this error: fatal: Unable to find destination for addr 0xNNN on bus system.membus A workaround for this issue is to increase the memory as discussed in the following posts http://www.mail-archive.com/gem5-users@gem5.org/msg04502.html http://www.mail-ar

[gem5-users] modifying trace messages

Hi Where can I customize the trace messages in the source files? I am executing --debug-flags=Exec --trace-file=trace.out ... -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] consistency issue with gem5

>you can use the util/tracediff script >(http://www.m5sim.org/Debugging#tracediff). It seems that I can not pass all parameters to command line. Currently, in my cmp.py, I have system.l2.prefetcher = Prefetcher() However in Caches.py, I have class Prefetcher(BasePrefetcher): type = 'StridePr

Re: [gem5-users] consistency issue with gem5

The simulator job is to *simulate* the given code. Otherwise, it will be extremely difficult to verify the code because everything is possible! Specifically for my prefetcher, assume the program code looks like this LD 0x90 ADD ... Assume my prefetcher, predict something else which is wrong. The

[gem5-users] consistency issue with gem5

Hi I have a concern about gem5 simulator consistency and will be glad for any help. Thing is, I have implemented two different prefetchers, but with the same binary and command lines, I see that different block addresses are accessed. However which block is accessed must be a function of the progr

[gem5-users] Issue with mounting the disk image

Hi Maybe the question is not directly related to gem5, but the problem is users (not sudoers) can not execute mount command because of the permission set by the so they can not mount the disk image. Has anyone faced such problem? -- Regards, Mahmood

Re: [gem5-users] Low IP for SPEC CPU 2006 benchmarks

An update to this issue is to hear a feedback from someone who uses ALPHA binaries in SE mode. X86 is not as rich as ALPHA. If IPC values are normal in ALPHA, then there is something wrong with X86 decoder. On 6/17/13, Manmohan Manoharan wrote: > > Jerry Backer students.poly.edu> writes: > >> >

Re: [gem5-users] "terminate called after throwing an instance of 'std::bad_alloc' " when using trunk

>Not really :). If you know precisely what I should type, I'll do it. Simply run "valgrind build/X86/m5.debug ." Note that you have to compile in debug mode and valgrind is slow. So you have to lower the fast forward and other times. On 6/4/13, Ali Saidi wrote: > > > Normally you see a bad_al

Re: [gem5-users] "terminate called after throwing an instance of 'std::bad_alloc' " when using trunk

Hi bad_alloc() messages usually means running out of memory. You can attach valgrind to find memory leakage. Hope that help On 6/4/13, Maxime Chéramy wrote: > Hi, > > I've just updated my instance of gem5 with the last changes from the > mercurial repo. The code still compile properly but when I

Re: [gem5-users] Meaning of "warn: instruction 'fld' unimplemented"

Hi That means specific floating point instructions are not implemented. So they are ignored. If your benchmark, uses these instructions a lot, then your results are not very representative. On 5/24/13, Maxime Chéramy wrote: > Hello, > > With a specific bench, I encountered the warnings: > > warn:

Re: [gem5-users] cc1plus:warnings being treated as errors

Hi Comment or remove the following line from src/SConscript new_env.Append(CCFLAGS='-Werror') Hope that helps On 5/16/13, Ranga, L Udaya wrote: > Hi, > > I get a lot of error messages while building gem5 which are related to > uninitialized warnings being treated as errors. I tried adding s

Re: [gem5-users] GHB prefetcher

This may be useful http://www.mail-archive.com/gem5-users@gem5.org/msg02490.html On 5/7/13, Xiangyang Guo wrote: > Hi, gem5-user, > > I take a look at the GHB prefetcher provided by Gem5 , I'm wondering if > this part is finished or not? It seems that the code is like a stride based > GHB prefetc

Re: [gem5-users] Splash2

There are some scripts in config/splash2. Have you tried them? On 4/21/13, Northwestern wrote: > Hi guys, > > Because nobody answer my question and I am still working on it. I decide > send my simple question again. Thank you for your help! > > Best, > Tony > > Begin forwarded message: > >> From:

Re: [gem5-users] Low IP for SPEC CPU 2006 benchmarks

Hi I confirm that for some benchmarks. However it is very hard to pin point the fault. The most probable thing is the incorrect implementation of some special instructions. For example, CFP benhcmarks uses some special instructions a lot. So if the instruction has not been implemented correctly, th

Re: [gem5-users] L1 cache miss count

Hi Regarding your first question, you can modify the code and print the stats to a file or std::cout whenever you want. Check and see where in the code, your desired miss stat is increased. On 3/8/13, tejasi pimpalkhute wrote: > Hi All, > > Could anyone please tell me if I can check the count of

Re: [gem5-users] Unimplemented Function

Hi What is the IPC you get from h264? On 2/4/13, Rodrigo Reynolds Ramírez wrote: > > Hello everyone, > I was using the stable version (f75ee4849c40), I download the version in > development (890fc69ba53c) and only one benckmark does not work. I suppose > this syscall will be supported in future r

Re: [gem5-users] memory management

ory system and making it incredibly large is just > covering the problem up. > > Ali > > On Feb 2, 2013, at 2:57 AM, Mahmood Naderan wrote: > >> It is really annoying. I think mmap is responsible for this behavior. >> >> On 1/31/13, Mahmood Naderan wrote: >&

Re: [gem5-users] memory management

It is really annoying. I think mmap is responsible for this behavior. On 1/31/13, Mahmood Naderan wrote: > Hi > I have found that in a N multicore simulation, defined memory size > should be N*4GB. For example, I am simulting eight cores so I have to > define 32GB memory. Otherwis

[gem5-users] memory management

Hi I have found that in a N multicore simulation, defined memory size should be N*4GB. For example, I am simulting eight cores so I have to define 32GB memory. Otherwise I randomly get "unable to find destination ..." error. However in reality while the simulation is running, "top" command shows t

Re: [gem5-users] Last leve cache accesses

I think so. However Andreas says MasterID is the right thing http://comments.gmane.org/gmane.comp.emulators.m5.users/13388 On 1/27/13, mihai pricopi wrote: > In cache_imple.hh access() function, is the returned value of > pkt->req->contextId() the id of the core who made the cache request > (assu

Re: [gem5-users] core id in PacketPtr

D. That includes DMAs etc. Thus, every > block that on its own generates requests should have a master id. > > Good luck. > > Andreas > > On 25/01/2013 10:56, "Mahmood Naderan" wrote: > >>I see this in stride.cc >> >>MasterID master_id = useMasterI

Re: [gem5-users] core id in PacketPtr

eld is hop to hop and is only used by (de)multiplexing > components to send responses to the right port. > > Andreas > > On 25/01/2013 10:27, "Mahmood Naderan" wrote: > >>Hi, >>How can I find which core send a message? As I read packet.hh, there >>is n

[gem5-users] core id in PacketPtr

Hi, How can I find which core send a message? As I read packet.hh, there is no member like core_id or something else. The only thing that I guess is /** * Device address (e.g., bus ID) of the source of the * transaction. The source is not responsible for setting this * field; it

Re: [gem5-users] prefetcher configuration has been changed

ok thanks. it seems that the prefetcher has to be defined in Caches.py as part of of "class L2Cache(BaseCache):" On 1/22/13, Nilay wrote: > > On Tue, January 22, 2013 1:33 am, Mahmood Naderan wrote: >> Hi >> it seems that the way we configure and define a prefetche

[gem5-users] prefetcher configuration has been changed

Hi it seems that the way we configure and define a prefetcher has been chnaged in the latest revision 9476. So far, my cmp.py looked like: system.l2 = L2Cache() system.l2.prefetcher = Prefetcher() and Caches.py looked like class Prefetcher(BasePrefetcher): type = 'StridePrefetcher' degre

Re: [gem5-users] Again... "Tried to write unmapped address"

Thank you. It is fine now On 1/21/13, Nilay wrote: > On Sun, January 20, 2013 2:14 pm, Mahmood Naderan wrote: >> Here is my findings: >> 1) for r9460, I get a segmentation fault (and not the unmapped >> address). I attached the gdb output and the config.ini and the config

Re: [gem5-users] Again... "Tried to write unmapped address"

By the way, I see that error for read/write/execute On 1/20/13, Mahmood Naderan wrote: > Hi, > With the latest revision on gem5, I get "Tried to write unmapped > address" for a number of spec2k6 benchmarks however I previous > revisions have no problem. > This time the

[gem5-users] Again... "Tried to write unmapped address"

Hi, With the latest revision on gem5, I get "Tried to write unmapped address" for a number of spec2k6 benchmarks however I previous revisions have no problem. This time the unmapped address is 0x58, 0xb8 or even 0x00!! REAL SIMULATION info: Entering event queue @ 23127352500. Starting s

Re: [gem5-users] How I compile the spec2006 binaries statically

Hi you have to modify the config files (the compiler and system you use) and add the -static option to the compiler flag and then build with runspec. On 12/6/12, mir shan wrote: > Dear members > I have licensed SPEC2006, I go through > http://www.m5sim.org/SPEC2006_benchmarks page but couldn't un

[gem5-users] flaoting point instructions

Hi Is there any plan to implement some floating point X86 instructions? fnstcw_Mw fldcw_Mw emms fwait There were some efforts but seems that they have not been committed to the repository. I remember a discussion on that. Any news? -- Regards, Mahmood

Re: [gem5-users] Where to change SimpleDRAM size

Thanks -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Where to change SimpleDRAM size

Hi How can I increase the size of a SimpleDRAM memory? in SimpleDRAM.py, I see only some timing parameters. -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] error setting --prog-interval

Didn't get the point! can you state an example? Doesn't "1" imply 1 ticks? On 11/23/12, Ali Saidi wrote: > You need at specify a time.. 1 has no units. > Ali > > On Nov 16, 2012, at 6:00 AM, Mahmood Naderan wrote: > >> Hi >> In the last

[gem5-users] error setting --prog-interval

Hi In the lastest revision, when I use "--prog-interval=1" or "--prog-interval 1" it says TypeError: wrong type '' should be str Error setting param AtomicSimpleCPU.progress_interval to 1 According to the Options.py, it should be integer. Why I receive that error? Regards, Mahmood __

Re: [gem5-users] Can Any one Suggest any good tool to Analyze the Source code

I use kdevelop and it is fine. Just import gem5/ and let it parse the source files. On 11/15/12, Steve Reinhardt wrote: > The .cc files are not "managed C++" (whatever that is), they're just plain > old C++. If your Eclipse or whatever doesn't recognize .cc files as plain > C++, you just need to

Re: [gem5-users] MSHR full status

>Does that mean for each core I have 10 mshrs Right >Also is there any way to differentiate which CACHE this MSHR belongs to, L1 >cache or L2 cache or others? There is a bool variable "isTopLevel" in cache_impl.hh that you can differenciate cache levels. For L1 it is 1 an for L2 it is 0. On 11

Re: [gem5-users] About L1 dcache prefetcher

So, you don't have system.cpu0.dcache.prefetcher ? On 11/8/12, IC wrote: > Hello, > > When I enable stride prefetcher on L1 dcache, and run timing mode on 4 > cores configuration, > > The stats.txt shows that only one core (core1) has prefetch statistics.The > number are zero on other core's pref

Re: [gem5-users] gem5-installation freezing

>bash: -/.bashrc: No such file or directory So you can create this file manually. >cp: cannot stat `/home/talpur/bench.c': No such file or directory Simple. You don't have `/home/talpur/bench.c'. check the path -- Regards, Mahmood ___ gem5-users mailin

Re: [gem5-users] gem5-installation freezing

>bash: -/.bashrc: No such file or directory So you are not using bash. what is you shell? csh? zsh?... -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] memory bandwidth

roller model, SimpleDRAM and configure > the timing accordingly. > > Andreas > > On 01/11/2012 20:52, "Mahmood Naderan" wrote: > > >Hi > >How can I calculate the PhysicalMemory bandwidth? Is that infinite in > >gem5? > > > >-- > >Regards,

[gem5-users] memory bandwidth

Hi How can I calculate the PhysicalMemory bandwidth? Is that infinite in gem5? -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] --debug-flag Cache trace file information

Basically, for every address you can do Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1); to find the block address. -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] --debug-flag Cache trace file information

That mesage is printed in cache_impl.hh (Cache::access). Just see the code and you will find that this is not the block address. -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] nan in stats file

>There are lot of statas with 0 value I mean which stat is nan? >For example, switch_cpu1.numCycles If that stat is zero, then it means you didn't switch the cpu from atomic to detailed or timing (though I don't kniw what you ran). -- Regards, Mahmood

Re: [gem5-users] nan in stats file

ate: Fri, 26 Oct 2012 09:47:30 +0200 > From: Mahmood Naderan > To: gem5 users mailing list > Subject: Re: [gem5-users] nan in stats file > Message-ID: > < > cada2p2v9ydfjrmya3wpwozvmug34r82vlfuysgpfkx43ubp...@mail.gmail.com> > Content-Type: text/plain; charset=

Re: [gem5-users] nan in stats file

Hi, Are these single stats or ratios? Regards, Mahmood On Fri, Oct 26, 2012 at 3:47 AM, Runjie Zhang wrote: > Hello, > > I simulated Parsec2.1 benchmark suites with X86_MOESI_hammer and O3 cpu. > I also dumpreset stats frequently to monitor processor activity. > > When I simulate only 1 c

Re: [gem5-users] Running List of Programs

If you search the list archive, you will find the benchamrks (from spec2k6) that are not runnable in SE mode. I think those syscalls for x86 are still unimplemented expecially the ones needed for CFP benchmarks. Some can be bypassed by simply ignoring the syscall or borrowing from ALPHA. -- Regar

Re: [gem5-users] How to compute CPU utilization rate from stats.txt

system.switch_cpus.idleCycles seems to be a new stat because I don't have that in my stats. If you are talking about "unscheduled due to idling", then I think you should look at idle cycles at IEW stage. If cpu is idle in decode stage, are you going to include that? -- Regards, Mahmood __

Re: [gem5-users] numThreads in BaseCPU.py

yes. If you want to change issue width, have a look at issueWidth in o3/O3PU.py -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Access icache every cycle

How about *not to* push cache latencies in to the queue? Though I am not quite sure about if this is correct. Regards, Mahmood On Mon, Oct 22, 2012 at 10:58 PM, Runjie Zhang wrote: > Greetings, > > I tried to write stressmarks in X86 assembly so that the simulated IPC > or O3CPU can hit N f

Re: [gem5-users] Problems with McPAT and gem5

I remember that "Andreas Hansson" said a json format is under development which will close the gap between gem5 and mcpat. Any news for that? Regards, Mahmood On Mon, Oct 22, 2012 at 3:44 AM, Amin Farmahini wrote: > Hi Hongyuan, > > I wonder if you have made any progress on using the McPAT sc

Re: [gem5-users] stats.txt

src/base/stats/text.cc what do you want to do? Regards, Mahmood On Tue, Oct 16, 2012 at 11:47 PM, Tianwei Zhang wrote: > source file ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] PARSEC compilation problem

PARSEC has its own mailing list. Regards, Mahmood On Mon, Sep 24, 2012 at 11:11 AM, Ardalan Pouya wrote: > Hello everyone , > I am building PARSEC benchmark and having this error please help me to > solve it : > (OS is Ubuntu 11.04 and I upgraded the openssl to it's latest version) > > > md5-x

Re: [gem5-users] Dealing with a full prefetch queue

ew of the prefetch traffic. Regards, Mahmood On Wed, Sep 19, 2012 at 12:13 PM, Nilay Vaish wrote: > On Wed, 19 Sep 2012, Mahmood Naderan wrote: > > Hi >> In the default prefetch code of gem5, we see >> >>// We just remove the head if we are full >>

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