[gem5-users] Strange behavior ARM 32-bit machine

Hello, I've been facing a strange behavior with the --machine-type=VExpress_EMM option in FS mode. In a very simple configuration, I run a bench that should run 20M instructions (checked in an ARM board). With this machine although, it runs 170-350 M instructions. Even if the result of the executi

Re: [gem5-users] PARSEC3.0 and new m5op pseudo-instruction issue

Hello, You have to link m5op_arm.S, not compile it. There should be a flag (LDFLAGS maybe) where you can pass m5op_arm.S. Another possibility is compiling it as a library. Check utils/m5/Makefile.ARCH. Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2017-02-23 1

Re: [gem5-users] Why Two Parameters Do Not Take Effect

Hello, Number of cache ports is supposed to limit the number of store writes to the L1D cache. Maybe you need a wide pipe to notice any change of this param. I'd suggest varying it between 1 and 4 depending on the aggressiveness of your configuration. Regards, -- Fernando A. Endo, Post-doc INRI

Re: [gem5-users] [gem5-dev] Question about arm/neon instruction timing in gem5

Hello, I'm redirecting the question to the right mailing list, > 1.- ARM's documentation (Cortex™-A9 NEON™ Media ProcessingEngine) provides instruction timing tables for VFP and NEON instructions. According to those tables VFP and NEON instructions have different timing values, for example the VF

Re: [gem5-users] Number of instructions Vs number of ticks + resetstats + checkpointing

Hello, >1. reset the stats and checkpoint, both after 10M instructions You don't need to reset the stats before taking a checkpoint. There is the option --at-instruction that let you interpret some command line options in committed instructions rather than gem5 ticks. If it is convenient to you,

Re: [gem5-users] Inconsistent big integer multiplication results comparing physical machine with full-system simulation mode

Hello, Probably I don't have all the info, but I had the following questions: Do you really need to compile and debug (e.g., run gdb) in the guest environment ("inside the gem5 FS linux")? Would not comparing the HW results with the gem5 traces in Atomic mode be enough? Regards, -- Fernando A. E

Re: [gem5-users] Source and Destination Registers in StaticInst

Hello, The program src/arch/isa_parser.py is supposed to translate .isa files to generated .cc/.hh ones. Try to grep your instructions in build/ARM/arch/arm/generated/decoder-ns.*.inc, so you can see the generated files where _destRegIdx and _srcRegIdx are filled. Regards, -- Fernando A. Endo, P

Re: [gem5-users] Further understanding of exec debug trace

Hello, Did you try to disassemble your binary under simulation and grep the addresses to check if they're there? I'd say that 0x is from the user program. Longer addresses should be from the kernel (considering my experience with gem5/ARM). @(function name) could be from any piece of program

Re: [gem5-users] vector (NEON) instructions missing in execution trace

and how they work? > > Regards, > Raul. > > > -- > *From:* gem5-users [gem5-users-boun...@gem5.org] on behalf of Fernando > Endo [fernando.en...@gmail.com] > *Sent:* Thursday, November 10, 2016 3:28 PM > *To:* gem5 users mailing list

Re: [gem5-users] vector (NEON) instructions missing in execution trace

Hello, It seems that you're compiling for 32 bits processors, but for reference in gem5/AArch64 the SIMD mnemonics may be exactly the same as the SISD ones, sometimes only the register naming changes. It can be quite confusing to understand at first, indeed these parts of the code could be refacto

Re: [gem5-users] How to generate utilisation statistics of the arm register file and neon register file

Hello, Which model are you intending to use? In the O3 model, the INT and FP/NEON register files are separated. But, I think that although SIMD accesses (INT and FP) are included in FP reg file stats, each SIMD uop actually reads and writes several FP registers, so they are counted multiple times

Re: [gem5-users] ARM config error

Hi, As the error says, there is a stat config being initialized with negative values, which are forbidden. Try to run: gdb --args $GEM5_COMMAND_LINE run bt to see where the error comes from. Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2016-09-13 16:45 GMT+

Re: [gem5-users] Set DRAM Latency when using it with O3_ARM_v7a.py

Hello, For a Cortex-A9, most DRAM params may be the same as a DRAM for a PC, but not the size and frequency as Anoir want. The DRAM latency cannot be set explicitly, because it varies depending on several factors and other params (https://en.wikipedia.org/wiki/Memory_timings). In the DDR4_2400_x6

Re: [gem5-users] Warning when executing with cpu-type=detailed

Hello, The option --cpu-type=arm_detailed already does what you want. (./build/ARM/gem5.opt configs/example/se.py --list-cpu-types) In general you can ignore that kind of warning. They are related to some processor special registers/coprocessors access. Hope it helps, -- Fernando A. Endo, Post-d

Re: [gem5-users] fault injection into gem5 register?

Hello, You can look at src/cpu/SConscript and check if some debug flag dump branches. You can also create a new flag based on existing DPRINTF in the source. Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2016-08-15 3:24 GMT+02:00 李阳 : > Hi all, > > I am doing

Re: [gem5-users] warn: Returning zero for read from miscreg pmccntr

Hello, This is a link error. You should add m5op_arm.S or libm5.a (gcc -lm5) in your makefile. Look at util/m5/Makefile.arm to build the m5 library. Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2016-08-13 23:16 GMT+02:00 anoir nechi : > > > > > *Hi again Osc

Re: [gem5-users] SIMD for floating points instruction in ARM

Hello, Yes, gem5 supports (by default) FP SIMD instructions for both ARMv7 and ARMv8. The FP vector mode seems to be an outdated feature in which SIMD was emulated in SISD hardware. Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2016-08-09 11:16 GMT+02:00 anoi

Re: [gem5-users] How to run identical workloads with different phases in GEM5 SE mode?

Hello, What I'd do is have access to perf counters inside the application to monitor how many insts have been executed. When it goes past 100 M, trigger the second app. Perf counters work in AArch64 , but only in Full-system. You could also modify the pseudo-instruction 'rpns' to return the numbe

Re: [gem5-users] Setting cpu.numPhysFloatRegs to lower limit results in extremely slow simulation

Hello, The fact that 161 works is very strange. <163 must not work at all. In gem5/ARMv8 all FP and SIMD instructions allocate 4 destination registers, to correctly mimic one phys reg of 128 bits (the rename uses 32 bits phys regs for AArch64). This means that one must set numPhysFloatRegs=4*num_r

Re: [gem5-users] Gcc 4.8.5 for Alpha

Hello, I assume that the Alpha support in gcc was droped a long time ago, so backporting it to a very recent gcc may not work. Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2016-07-12 23:09 GMT+02:00 Ayaz Akram : > Thanks, Andreas. Actually I needed to test s

Re: [gem5-users] PARSEC-GEM5-fullsytem error while running benchmark

Hello, Are you sure that ./streamcluster actually works? Running it in an emulator such as QEMU (if Alpha is supported...) would be useful to know if the segfault is caused by gem5. Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2016-07-11 12:47 GMT+02:00 <206

Re: [gem5-users] Operation Classes in Arm

we can incorporate your work! > > Cheers, > Jason > > On Sat, Jul 9, 2016, 8:08 PM Ayaz Akram wrote: > >> Hi Fernando, >> >> Will it be possible for you to post the relevant code here ? That will >> just save some of my time. >> >> Thanks >&

Re: [gem5-users] Application output not stored to the disk image with COW layer off

Hello, It seems to be a bug for me. Try to grep "/sbin/m5 readfile" in your gem5 disk image, e.g., inside aarch64-ubuntu-trusty-headless.img it is at /etc/init/tty1.conf. That command loads the script passed with --script, so maybe the bug is by there. Hope it helps, -- Fernando A. Endo, Post-do

Re: [gem5-users] Operation Classes in Arm

Hello, I completely agree that FP and SIMD should have different opClasses. I actually separated them, but didn't posted the patch yet (it is not that difficult). Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2016-06-29 16:59 GMT+02:00 Ayaz Akram : > I have a

Re: [gem5-users] gem5 stats for total instruction executed

Hi, Probably you'll have to check by yourself if sim_insts gives the stat that you want (i.e., total committed instructions since gem5 started). It seems that they've recently patched this stats. Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2016-06-09 16:10 G

Re: [gem5-users] Running an RTOS on Gem-5

Hello, I think that you should be familiar with how to port freeRTOS or any OS to a real platform (which already involves a non negligible amount of work). Then, you'll need to use the --bare-metal option in gem5/FS mode to be able to boot another OS other than linux. Knowing if freeRTOS run in CP

Re: [gem5-users] Do the caches resets every time a checkpoint is created?

Hello, It seems to me that the cache state is not saved in checkpoints, while the TLB state is. What people usually do is warmup the processor. Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2016-05-06 23:16 GMT+02:00 Nimish Girdhar : > Hello all, > > If I run

Re: [gem5-users] Repeated switching between timing and atomic

Hello, The concerned file is configs/common/Simulation.py. Probably the mix "--repeat-switch=10 --cpu-type=atomic --restore-with-cpu=timing" is not well supported/tested. Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2016-05-04 12:26 GMT+02:00 Tanmay G

Re: [gem5-users] SIMD instructions on Arm

Hello, You can try to set with -mcpu a CPU that does not support the SIMD extension at all. There may also be FP instructions that are wrongly (or for simplification purposes) tagged with SIMD opClasses in gem5. Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2

Re: [gem5-users] fastforwarding and maxinsts options in FS mode

Hello, An approximate way is to checkpoint the begining of the benchmarck ("m5 checkpoint" in the .rcS before calling the bench), then restore with -F (fast-forward) or -W (warm-up). If you need the switch in a very precise point in the bench, you can try to restore with -F and inser

Re: [gem5-users] commnad line options for Full System Simulation

Hello, I always export those variables and pass the --disk-image=/path/disk.img and --kernel=/path/vmlinux in the command line. You need --script to set your workload through a rcS script, there are examples in configs/boot/. In FS mode, gem5 simulates TLBs. Regards, -- Fernando A. Endo, Post-do

Re: [gem5-users] simulation crashes on timebuffer for 4wide configuration

Hello, As a rule of thumb, *ComSize should be greater than any *Delay parameter. Time buffers are communication queues between stages, used to mimic substages and deeper pipelines than 7 or so. Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2016-04-17 16:28 GMT

Re: [gem5-users] Instruction trace address for ARM architecture

Hello, Some helper functions like _start may generate thumb or arm instructions if the CPU support them, even if you set -marm or -mthumb. It'd better if you could set a CPU that only run the ARM 32-bit ISA. Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2016-0

Re: [gem5-users] ARMv7 pli instruction implementation

Hello, You have to check if gem5 implements the 'pli' instruction or if it is simply ignored at early stages (if you're using the O3/Minor model). It'd be interesting the check if 'nop' instructions are accounted or not in sim_insts. Regads, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne A

Re: [gem5-users] Instruction counters

explanations, please? > > Thank you > > +---+ > | Louisa Bessad | > | PhD student - LIRMM - Sysmic | > | Bâtiment 4 Bureau 2.92| > +-------+ > > Le 19/03/2016 13:50, Fernando Endo a écrit : > > Hello, > > >

Re: [gem5-users] gem5 and McPAT (II)

Hello, McPAT can be a nice tool to quickly get rough estimations of energy consumption. It should be used with care, ensuring that your simulations/comparisons are meaningful. I worked with both gem5 and McPAT during my thesis, so if you need information about their integration: https://tel.archi

Re: [gem5-users] Instruction counters

Hello, If the section of code is executed only a few times, it is easier to call m5_resetstats and/or m5_dumpstats at the begining and the end of the section. You're probably summing the number of issued uops (i.e., system.cpu.iq...IntAlu, etc), the sim_insts refers to the committed instructions

Re: [gem5-users] About Prefetchers in Cache

Hello, To my understanding, TaggedPrefetcher is a next-line prefetcher. Only StridePrefetcher and TaggedPrefetcher are intended to be declared in the .py config files. For an L3, I'd use a next-line prefetcher with degree=1. Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantiqu

Re: [gem5-users] Checkpoint in detailed cpu causing error

Ah, it is likely that you may have problems with pending interruptions and the like, if you want to restore the checkpoint later. -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2016-02-28 13:34 GMT+01:00 Fernando Endo : > Hi again, > > Sorry, I misunders

Re: [gem5-users] Checkpoint in detailed cpu causing error

Hi again, Sorry, I misunderstood your initial question. So, if you want to take a checkpoint without draining the O3 pipe, then you need to get the architectural state (committed information). Context 0 is ok for single-core simulation. It seems that readIntReg reads the physical registers, so be

Re: [gem5-users] m5 utility: exit with error

Hello, You have to pass the command itself to 'm5': ./m5 exit ./m5 resetstats (If you manually booted linux in the FS, maybe 'sudo m5 checkpoint' is needed) It assumes delay=0/period=0 if nothing is given. Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2016-0

Re: [gem5-users] Differentiating user mode stats from kernel mode stats

Hi, I remarked that there is an option called "--enable-context-switch-stats-dump" (my gem5 version: 11153:20bbfe5b2b86). Maybe, you can take it as a starting point to implement what you need. Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2016-02-23 9:46 GMT+0

Re: [gem5-users] cache misses in gem5

Hello, You'll need to use the option '--debug-flags=' (to dump the messages in DPRINTF statements) and eventually create/modify DPRINTFs to dump the instructions missing the cache. Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2016-02-17 8:43 GMT+01:00 Manoj B

Re: [gem5-users] Add new Functional Unit to x86

Hello, The notion of functional unit and instruction set are decoupled in gem5. The ISA description is in src/arch, where instructions receive an 'op_class' tag, e.g., IntAluOp. The opClasses are defined both in src/cpu/FuncUnit.py src/cpu/op_class.hh. Regards, -- Fernando A. Endo, Post-doc INR

Re: [gem5-users] Checkpoint in detailed cpu causing error

Hello, Maybe this workaround could work for you: simulate until the bench ends, switch to the atomic CPU and take a checkpoint. The switch from detailed to atomic works (my gem5 version: 11153:20bbfe5b2b86). You'll probably need to modify configs/common/Simulation.py to do that. Hope it helps an

Re: [gem5-users] Access devices on gem5 full system booting cut down linux image

Hello, > b) is it possible to use ArmKVMCPU model on x86 host via QEMU ARM virtualization?? I was thinking to emulate ARM platform on my linux-x86 host first and then run gem5 in that QEMU VM. Can I use ArmKVMCPU in that case because if I can then I expect some speed improvements Qemu does not su

Re: [gem5-users] using a different arm linux kernel

Hello, Your problem may be a kernel related one. Asking the question in the related maling-list is one option. Some kernels (or configurations) map disks to /dev/hd* for example. Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2015-12-23 18:03 GMT+01:00 Khaled A

Re: [gem5-users] Kernel panic while trying to boot ARM FS

Hello, This happens because in the bootargs "root=" is wrong or the kernel could not bring up the disk device. Did you set "root=/dev/sda1"? Is the disk partition type in sda1 supported by your kernel? Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2015-12-21 1

Re: [gem5-users] How to extract TLB accesses in X86 Ruby for McPAT integration

Hello, Note that, in the SE mode, there are no TLB stats. In FS there are. Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2015-12-21 14:53 GMT-02:00 Yaswanth Akaveeti < yaswanth.akave...@mail.mcgill.ca>: > Hi all, > > > I simulated 2-core O3 X86 system in FS w

Re: [gem5-users] Compile error on ARM arch machine

Hello, You should look for the files installed by the 'kvm' or related packages. If one of them also point to /usr/include/linux/kvm.h, this means that the corresponding package is outdated or does not correspond to your kernel version. Seeing if your board supports VGIC_V2 is something to check t

Re: [gem5-users] Memory errors while running gem5

Hello, You should better use an arm-*-linux-gnueabi. In the SE mode, gem5 emulates an Linux environment, so you need a toolchain that consider this environment too. Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2015-12-09 0:23 GMT+01:00 Ejjeh, Adel : > Hello

Re: [gem5-users] listing executed functions

Hello, gprof can also do that if you don't have self-modifying code that creates functions Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2015-12-11 9:35 GMT+01:00 Andreas Hansson : > Hi Kany, > > Simulated, or on the host? > > callgrind should help you, just

Re: [gem5-users] CPI in TimingSimpleCPU model with memory systems

Hello, CPI should be numCycles/committedInsts You can also check the code of the stat computation in the O3CPU, for example. Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2015-12-08 12:06 GMT+01:00 Will : > Hello, > > I have built SPEC2006 configured with AR

Re: [gem5-users] Fwd: Adding Custom Instruction in ARM ISA

Hello, Im my opinion, you have only to change the code in src/arch/arm/, except if you want to create a new opClass. Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2015-12-11 5:24 GMT+01:00 Hemendra Rawat : > Hi All, > > I want to add few custom instructions i

Re: [gem5-users] How to associate stats printings to m5ops in FS mode?

--- End Simulation Statistics - >> >> >> [2] Please see the answer (Where Andreas has explained the fact) to this >> question: >> >> http://comments.gmane.org/gmane.comp.emulators.m5.users/18824 >> >> >> [3] Please see the answe

Re: [gem5-users] using a different arm linux kernel

Hello, A quick tip would be copying the config of the released ARM linux kernel in the website and pasting as .config in the new kernel source. You should run 'make menuconfig' to adjust the .config to the available options (semi-automatic process) and then enable GTS. You can also copy-paste the

Re: [gem5-users] How to associate stats printings to m5ops in FS mode?

Hello, Please, could you give us more information or/and an example of what you're observing? Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2015-12-02 6:19 GMT+01:00 Tod : > Hi everyone, > > > In SE mode, it's much easier to associate each stats printing to i

Re: [gem5-users] KVM, ARM64, GEM

Hello, I'm still trying the KVM cpu for ARM. As far as I can understand: 1) You have to install a linux kernel in an ARM board, both suppoting virtualization/kvm 2) Your bootloader/bootstrapper should enable the Execution Level 2 (hypervisor mode) in your ARM processor before calling the Linux ke

Re: [gem5-users] Cortex-A53/57

Hello, My guess is that their configuration are kind of 64-bit versions of the Cortex-A7 (==A53) and Cortex-A9 (==A57). The A53 is in-order and should be simulated with the MinorCPU, while the A57 with O3CPU (out-of-order). Also, the A53 is dual-issue (the A7 is partial dual-issue). Regards, --

Re: [gem5-users] Getting error Can't find file 'vmlinux.aarch32.ll_20131205.0-gem5' on path

Hello, I'd suggest to do this in the gem5 dir: ln -s ../linux-linaro-tracking-gem5/ binaries Hope it works, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2015-11-14 9:03 GMT+01:00 rahul shrivastava : > Hi All, > > It seems that the above file does not exist at all an

Re: [gem5-users] InOrder ARM processor

Hello, You can use the MinorCPU model with for example: build/ARM/gem5.opt configs/example/se.py --cpu-type=minor -n 1 --caches --l2cache ... Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2015-11-05 12:48 GMT+01:00 Khaled Attia : > Hello, > I was wondering i

Re: [gem5-users] ARM cortex A-15 configuration

; > Now the results look similar to the real platform. So i am not sure how > far > > the cortex-A15 settings mentioned in [1] is correct. > > > > Thanks, > > Prathap > > > > > > On Sun, Nov 1, 2015 at 5:49 AM, Fernando Endo > > wrote: > > &g

Re: [gem5-users] ARM cortex A-15 configuration

Hello, Regarding [1], the instruction latencies of a A15 can be set as those of the A9 in [2], or as those of an A72 ( http://infocenter.arm.com/help/topic/com.arm.doc.uan0016a/cortex_a72_software_optimization_guide_external.pdf ) Best regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagn

Re: [gem5-users] How to increase critical path delay to model presence of aging

Could you develop a bit more your question? -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2015-09-27 13:48 GMT+02:00 f.nakhaee : > I want to determine the output quality if critical path violation occurred > in the presence of aging. For this reason I want to know if it

Re: [gem5-users] ARM LPAE and Linux binaries

Hello, LPAE seems to be a Kernel feature, hence you may need to recompile your Linux Kernel with the right flag config. You can also look for precompiled kernels in ARM Linux communities (linaro, Ubuntu, Debian). Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2

Re: [gem5-users] Timing in System Emulation (SE)

Hello, You can use the gem5 instruction rpns() (from util/m5/m5op.h) in your code, as if it was a gettime or cycle counter. It gives the nanosecs elapsed since the begining. Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2015-09-04 22:59 GMT+02:00 Marcos Horro

Re: [gem5-users] aarch64 (armv8-a) - question on adding a new processor support

Hello, 1. arm_detailed can be used to run aarch64 2. the config file is configs/common/O3_ARM_v7a.py Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2015-09-02 11:05 GMT+02:00 Virendra Kumar Pathak : > Hi gem5 group, > > I am new to gem5 and working on adding

Re: [gem5-users] How to run Timing CPU model in gem5

Hello, It seems to be a compilation related issue. If pthread.o is replaced by -lpthread it may work. Note that pthread.o may be a gem5 modified threading library. Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2015-09-02 9:56 GMT+02:00 Azadeh Shirvanian : > H

Re: [gem5-users] Changing ARM pipeline configuration

Hello, I assume that back-end pipe widths (issue, wb, commit and squash) are the same. For a 2-way processor, an issue-width of 4 can be fine. Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2015-08-28 1:56 GMT+02:00 Rizwana Begum : > Hello All, > > I am trying

Re: [gem5-users] full-system simulation using custom kernel

Hello, Generally speaking about Linux, you can use a custom kernel with any compatible file system given that you copy paste the kernel modules (into /lib/modules) and fix the initialization process (initrd, init ram disk, etc). Regards, -- Fernando A. Endo, PhD student and researcher Universit

Re: [gem5-users] x86 Assertion `skidBuffer[tid].size() <= skidBufferMax' failed.

Hello, It seems that you're running a FS simulation, that's why those event messages appear. Skid buffer are intended to temporary hold instructions comming from an earlier pipe stage when a pipe stall happens. Nevertheless, it is strage for me that increasing the issue width alone produces overfl

Re: [gem5-users] How to add additional port to memory?

Hello, If you want your pipe to perform two memory operations per cycle, you can increase the number of load/store execution ports (functional units). The pipe should also have enough buffering structs to support the extra multi-issues loads/stores (e.g. LSQs, MSHRs, WBs). I'm not aware if the cac

Re: [gem5-users] FS Checkpointing Hangs (ARM ISA)

Hello, In a old gem5 stable release, I managed to checkpoint the simulation with 'sudo m5 checkpoint'. If it does not work in a script, you can try to manually login and type the commands. Hope it helps, -- Fernando A. Endo, PhD student and researcher Université de Grenoble, UJF France 2015-0

Re: [gem5-users] A query regarding cross compilation of the kernel for ARM FS simulation

Hello, First, there are two different things: compiling the kernel, and compiling the root file system. If you want to run apps with hard float/soft float, you have to compile your file system libraries (eventually the native compiler too) with hard or soft float support, accordingly. If you com

Re: [gem5-users] Query regarding --script option passed as parameter to fs.py for ARM FS simulation

Hello, When you run a script, the login is automatic. To login, run the FS simulation without script. I'm not completly sure, but if your script does not have an 'm5 exit' or if it crashes, then linux will restart your script. Regards, -- Fernando A. Endo, PhD student and researcher Université

Re: [gem5-users] McPAT Peak Dynamic and Runtime Dynamic power

Hello, The peak dyn power is independent of utilization stats. It is computed by considering that each component is accessed at its maximum rate. Runtime dyn is equal the energy consumed divided by the time elapsed. Hope it helps, -- Fernando A. Endo, PhD student and researcher Université de G

Re: [gem5-users] Instruction trace as input to GEM5

Hello, Can QEMU dump translated binary machine instructions? If so, the binary dump could be inserted in an elf (I personally have never manipulated elf files, but there are a lot of conventions, e.g. function call, stack management, etc) Regards, -- Fernando A. Endo, PhD student and researcher

Re: [gem5-users] Understanding Instruction Traces

Hello, I'm not familiar with the instruction trace shown, but I'm my opinion, 'D' is for data and 'A' for address. It seems that they represent a common bus relying all execution units, then 'D' always have in the traces the last result processed. Again, this is a hypothesis. A memory access in t

Re: [gem5-users] Definition of "width" in gem5

Hello, To my understanding, width of pipeline stages is in uops. Regards, -- Fernando A. Endo, PhD student and researcher Université de Grenoble, UJF France 2015-05-25 2:06 GMT+02:00 Ayaz Akram : > I have a very basic question, Is width defined in terms of No. of > Instructions always? For i

Re: [gem5-users] Gem5 boot time

Hello, What matters the most for simulation speed is the gem5 CPU model. It seems that you're trying to boot with a detailed one. If the boot is not usefull for you, then consider a fast-forward option. Regards, -- Fernando A. Endo, PhD student and researcher Université de Grenoble, UJF France

Re: [gem5-users] profiling benchmarks with arm in full system mode

Hello, To me it seem doable, but I haven't tried yet. Please, consider that people in the mailing list are voluntiers, sometimes spending their free time to help others! Regards, -- Fernando A. Endo, PhD student and researcher Université de Grenoble, UJF France 2015-05-04 11:46 GMT+02:00 ESP

Re: [gem5-users] gem5 and AMP

Hello, >I need to work with x86, the key idea is to have complex cores without any modification and basic cores, the basic cores will not have floating point unit, branch predictors and a smaller private cache than complex cores. I'm not aware of x86 in gem5, but generally with the O3 model it se

Re: [gem5-users] ISA and kernel issues for ARM model

Hello, The "panic: Attempted to execute unimplemented instruction 'mrc'" message means that your code is trying to access a coprocessor. You have to check if your code can run in the FS mode. To run your own OS, the 'baremetal' option may be interesting in the FS mode, but I've never tried. Hope

Re: [gem5-users] "stack smashing detected" when built x86 full system

Hello, My guess: "stack smashing detected" probably means that you're running out of RAM memory or that your code is somehow overwritting the memory region reserved for the stack (I'd say that if one tries to do so in the userspace, a segfault would happen instead). Regards, -- Fernando A. Endo,

Re: [gem5-users] why miss latency cycles for ICache is greater than number of cpu cycles simulated

Hello, It's likely that the latency is in picoseconds. The system.cpu.numCycles is in CPU cycles. Regards, -- Fernando A. Endo, PhD student and researcher Université de Grenoble, UJF France 2015-04-18 1:27 GMT+02:00 Naveed Ul Mustafa : > > Hi all, > > I want to calculate the portion of total

Re: [gem5-users] arm-none-linux-gnueabi version?

Hello, Linux kernels usually only compile with well defined toolchains. Regards, -- Fernando A. Endo, PhD student and researcher Université de Grenoble, UJF France 2015-04-20 21:21 GMT+02:00 Dao Lu : > HI, > > On the tutorial where it has the following steps, > > *Now, to build the 2.6.35 ke

Re: [gem5-users] Out-of-order-memory execution architecture support

Hello, If you want to know if memory accesses can be performed out-of-order, then the answer is yes in the O3 CPU model. Regards, -- Fernando A. Endo, PhD student and researcher Université de Grenoble, UJF France 2015-04-20 15:04 GMT+02:00 Abhishek Joshi : > Does gem5 simulate any Arm implem

Re: [gem5-users] Implementing a queue for getting direct values for load instruction

Hello, I think that loaded data go directly to the register file. Regards, -- Fernando A. Endo, PhD student and researcher Université de Grenoble, UJF France 2015-04-19 18:42 GMT+02:00 Sreejith K M : > Hi all, > >I want to give the memory load values directly from a queue to simulate > a

Re: [gem5-users] Arm_detailed cpu - Explaining fetch rate from stats file

Hello, Depending on the ILP of the code and the depth of your EXE stage (indirectly modeled in gem5 through instruction latencies) an IPC around 0.7 can be a good performance. Sometimes the issue is blocking just because it is waiting for results. I'm not sure if such stalls explicitly appear some

Re: [gem5-users] Bare Metal FS mode query

Hello, I think that happens because usually gem5 in FS is used to boot Linux, so they considered that there is always a disk with a file system! I never tried the --bare-metal flags, but I think that if you don't bootstrap the disk, it is going to be ignored. Regards, -- Fernando A. Endo, PhD st

Re: [gem5-users] Writeback event takes more than 900 cycles in ALPHA

Hello, Memory accesses that miss the caches and TLB may take a very long time to commit. Depending on your configurations (CPU clock/mem latency) what you're seeing may happen. Regards, -- Fernando A. Endo, PhD student and researcher Université de Grenoble, UJF France 2015-04-03 18:50 GMT+02:

Re: [gem5-users] Fast forwarding after checkpoint

Hello, Not sure if the following ideas works. You could determine how long OS command are executed after the checkpoint and run a resetstats (eventually with a delay). You could try to use the fast forward flag (-F $INSTRUCTIONS) or the cache warming one, to fast-forward. Best regards, -- Ferna

Re: [gem5-users] In Order and O3 CPU

Hello, If you're not doing so already, I'd recommend to start with a known working configuration and incrementally change it toward your desired system. Then it'd be easier to report what piece of configuration is not working. Hope it helps, -- Fernando A. Endo, PhD student and researcher Unive

Re: [gem5-users] How to compile thread info into linux kernel

Hello, It seems to be a Linux kernel panic message, not a gem5 error. If that is the case, and if gem5 supports the feature, you should recompile the Linux kernel with the right option. Recompiling a kernel my be painful if you've never done that. Regards, -- Fernando A. Endo, PhD student and re

Re: [gem5-users] Running LBM benchmark on ARM gem5 SE mode

Hello, You can try to increase the memory size in python scripts in the configs/examples/se.py or through command line. Regards, -- Fernando A. Endo, PhD student and researcher Université de Grenoble, UJF France 2015-03-10 3:40 GMT+01:00 Vanchinathan Venkataramani : > I'm trying to run two i

Re: [gem5-users] Weird Parsec Simulation Result

Hello, Did you check the results to see if it is not bugging? What about cache miss rate? In my FS simulations, I usually insert 10s of sleep, because Linux may keep cpus busy with background stuff. Anyway, almost 100% of idleness is quite strange. Regards, -- Fernando A. Endo, PhD student and

Re: [gem5-users] Using gprof in SE mode

Hello, My guess is that it may not be possible, because gprof uses the OS interruptions to profile your code. Given that in the SE mode, syscalls are emulated by the host (http://en.wikipedia.org/wiki/Gprof), even if it works the results would be wrong. Regards, 2015-02-12 19:20 GMT+01:00, Raul

Re: [gem5-users] Segmentation fault in running FFT

Hello, Not sure if this is your problem, but If the crash comes from misaligned loads, you can try to align you data structures with compiler directives (e.g., #pragma in C or __attribute__ in gcc). You can also try gdb to check where in the code it happens (yes, inside the FS mode). Regards, 2

Re: [gem5-users] Map threads onto cores

Hello, You can check: 1) How many cores there are in the config.ini (or equivalent) file 2) How many cores the kernel detects during boot time (system.terminal file: [0.060288] Brought up 2 CPUs) Regards, 2015-01-31 10:53 GMT+01:00, Tayebe Sadeghi via gem5-users : > HiExcuse me,i have a pro

Re: [gem5-users] McPAT: number of cache levels

Hello, To my understanding, number_cache_levels reflects what you said in number 1. In number 2, I personally only tried number_of_L2s=1. When you mention that no power difference was observed with and without L2 cache, did you see the L2 cache in the McPAT output file? If you don't have detailed

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