[gem5-users] Re: Yet another question on implementing new instructions (ARM)

Hello Pedro, From the microarchitecture side, it is an implementation choice, and both (2x128 or 1x256) would be valid, each likely having its own complications. From the gem5 perspective, I am not sure why it was implemented this way, maybe this is simply representative of how most ARM micro

[gem5-users] Re: O3CPU Branch Predictor Similation

Hi Scott, As you correctly point out, the O3 model is being optimistic in its assumptions. It is even more optimistic in the sense that instruction fetch deals in micro-ops and not in architectural instructions (although most often one arch instruction will yield one micro-op). Therefore, th

[gem5-users] Re: statistics on gem5

On 5/6/21 10:47 AM, FARIDEH ZIAEE via gem5-users wrote: Hi, I have the following  questions  about simulation statistics: final_tick                 9724380737064 host_inst_rate        79246 host_mem_usage  1185244 host_op_rate         87406 host_seconds       68211.69 host_tick_rate    1292051

[gem5-users] Re: Converting KVM-taken checkpoint to atomic-needed checkpoint

I do not think IPC is supposed to make any sense with Atomic CPU anyway. One solution to check that it is running fine would be to go and check the output (stdout or a file), which seems doable for a microbenchmark, but maybe not for a large workload. Arthur On 4/15/21 5:18 AM, Majid Jalili v

[gem5-users] Re: The sim_insts in stats.txt under O3 type seems to be wrong

What does instsCommitted say (in the O3 stats)? Arthur On 4/8/21 4:30 AM, Liyichao via gem5-users wrote: Hi all: When I use se mode to execute an ELF under O3 type with Exec debug flags, the sim_insts in stats.txt is different with the lines of Exec debug output file. Sim_i

[gem5-users] Re: can anyboby tell me how to generate the checpoints of spec2017?

Hi, I think you will need to provide more context than this. We cannot help if we just know you encountered "a strange error". Namely, if you are running FullSystem or SystemEmulation, what ISA, the command lines, etc... Arthur On 4/8/21 3:59 PM, ?? via gem5-users wrote: hi, everyone, ?0?

[gem5-users] Re: How to use the KVM CPU take simpoint

KVM runs on the underlying processor (it's running the benchmark instructions 1:1 on the host CPU). As a result, there is no instrumentation going on, and so KVM CPU cannot capture basic block vector information. That's why you have to do it with atomic CPU, or any other functional simulator (y

[gem5-users] Re: Flushing the Caches

Hi Sherif, Maybe the functionality is already there, but it may not be as easy as it sounds depending on what you mean by "flushing". Functionally invalidating cache lines is staightforward, but anything that is dirty in the cache should be written back, and this may be harder to handle especi

[gem5-users] Re: Cannot boot full-system aarch64

Hi Pedro, I'm running aarch64 FS so it's definitely possible (although I am on an older patch...). I can't really comment on your error except for the fact that this looks like a memory mapping issue. It could be worth looking at the patch history to see if something changed recently, just to

[gem5-users] checkpoint/simpoint repository

Hi all gem5 users, A while back, I had contacted the SPEC committee to ask what their stance was about sharing gem5 SPEC CPU checkpoints (I am not aware of any public repo of gem5 checkpoints but I might be wrong!) tl;dr : checkpoints can be shared as long as it is behind a password, and the

[gem5-users] Re: Preferred way of dumping checkpoints for Aarch64

Boya, thank you for the input. Do you have first hand experience with using the Graviton instances and kvm ? I am also not sure kvm can speedup basic-block collection, but at least it can speedup simpoint collection which is half of the time spent, so that's pretty decent !Best, Arthur P

[gem5-users] Preferred way of dumping checkpoints for Aarch64

-running workloads, like maybe using the kvm cpu model and a specific ARM dev board (but which one?) or server (then again, which one?). Any insight or methodology details is appreciated :) Best, Arthur Perais ___ gem5-users mailing list -- gem5-users@gem5

Re: [gem5-users] 答复: syscall set_tid_address (#258) unimplemented

^ make: *** [pthread.o] Error 1 At this moment, I do not see anything else I can do for m5threads.. -------- *发件人:* gem5-users 代表 Arthur Perais *发送时间:* 2016年12月21日 2:43:14 *收件人:* gem5

Re: [gem5-users] syscall set_tid_address (#258) unimplemented

Hi, You are running in system emulation mode (se.py), meaning that all calls to OS are emulated by gem5, and in particular, set_tid_address does not seem to be implemented. By any chance, is your code multithreaded? As is, system emulation does not support multithreaded code, so this might

Re: [gem5-users] O3 CPU register forwarding

W C Please correct me if I'm wrong. Then when the result of instr1 becomes available at its E stage, the I stage of instr2 can issued instr2 at the same cycle? Thank you, Fateme On Wed, Nov 23, 2016 at 12:23 PM, Arthur Perais mailto:arthur.per...@inria.fr>> wrote: Hello Fatem

Re: [gem5-users] O3 CPU register forwarding

Hello Fateme, I hope I got your question right, so let me try to answer. Short answer is gem5 o3 does not implement register forwarding. Long answer is that it kind of does if you keep a parameter set to one. If your issueToExecute latency is greater than one, then two dependent instructions

Re: [gem5-users] Timing about Branch Instruction in MinorCPU

I'm not particularly familiar with the Minor code, but let's go for the usual suspects. When you say 5 cycles on correctly predicted branches, is it an average, or is it for some branches? Is it for taken or non-taken? Could it be misses in the I-Cache/ITLB? Le 22/11/2016 à 11:49, Will a écri

Re: [gem5-users] Get gem5 CPU pipeline configuration

University of Illinois at Urbana-Champaign > Siebel Center for Computer Science > 201 N Goodwin Ave, Urbana, IL 61801 > > On May 26, 2016, at 10:00 AM, Arthur Perais < arthur.per...@inria.fr > > > wrote: > > > Hello Adel, > > > When you run a simul

Re: [gem5-users] Cache properties

Hi Murat, 1) As far as I am aware, only PIPT caches are implemented in gem5 (arguably the L1 can be VIPT as a result of using the correct combination of associativity/number of sets and page size). If you want a virtual cache, you'll have to implement it yourself, and this is not going to be t

Re: [gem5-users] Get gem5 CPU pipeline configuration

list gem5-users@gem5.org <mailto:gem5-users@gem5.org> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Arthur Perais INRIA Bretagne Atla

Re: [gem5-users] n155 register

Systems / /IIT Bombay / /Ph - 7506112155/ ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Arthur Perais INRIA Bretagne Atlantique Bâtiment 12E, Bureau E303, Campus de Beaulieu 35042 Rennes, France

Re: [gem5-users] SIMD instructions on Arm

am" > À: "gem5 users mailing list" > Envoyé: Samedi 30 Avril 2016 20:05:46 > Objet: Re: [gem5-users] SIMD instructions on Arm > No, I am using system emulation mode. > Thanks > On Sat, Apr 30, 2016 at 2:02 PM, Arthur Perais < arthur.per...@inria.fr > >

Re: [gem5-users] SIMD instructions on Arm

Could the SIMD instructions be in the kernel/libraries rather than in your benchmark (I'm assuming you're using Full System). Best, Arthur. - Mail original - > De: "Ayaz Akram" > À: "gem5 users mailing list" > Envoyé: Samedi 30 Avril 2016 19:58:17 > Objet: [gem5-users] SIMD instru

Re: [gem5-users] o3cpu: cache ports

orts being able to read 2x32B and write 32B per cycle to their L1Cache (from http://www.realworldtech.com/haswell-cpu/5/ ). I don't know if this is steady throughput, but if it is, I suppose assuming 2 loads and 1 store per cycle is reasonable. > Regards, > On Tue, Apr 26, 201

Re: [gem5-users] o3cpu: cache ports

t;mailto:gem5-users-boun...@gem5.org>> on behalf of Arthur Perais mailto:arthur.per...@inria.fr>> Reply-To: gem5 users mailing list <mailto:gem5-users@gem5.org>> Date: Tuesday, 19 April 2016 at 10:41 To: "gem5-users@gem5.org <mailto:gem5-users@gem5.org>" mailt

Re: [gem5-users] gem5 CPU clock question

gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Arthur Perais INRIA Bretagne Atlantique Bâtiment 12E, Bureau E303, Campus de Beaulieu 35042 Rennes, France ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-

[gem5-users] o3cpu: cache ports

st, but it's really not. I can write a small patch for the first solution (don't increase "usedPorts" on load accesses), but I am not sure this corresponds to the philosophy of the code. What do you think would be the best course of action? Best, Arthur. -- Art

Re: [gem5-users] Different number of cache accesses on different cache sizes

ppens then. On 8 April 2016 at 13:15, Arthur Perais <mailto:arthur.per...@inria.fr>> wrote: Hi Felipe, I'm gonna assume that you run O3CPU or Minor. Changing cache size changes timing. Changing timing may change the number of loads that get their data from the Store Q

Re: [gem5-users] Different number of cache accesses on different cache sizes

of the program and it should also be independent of the architecture used. Thanks -- Felipe ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Arthur Perais INRIA Bretagne Atlantique Bâtiment 1

Re: [gem5-users] Low IPC Values of SPEC Benchmarks on O3X86 Architecture

tion and conflictingLoads vs. forwardedLoads stats). Also check that your issueToExecute delay is a single cycle. Hope it helps. Arthur Perais. *if I remember correctly, a single branch is three uop, so if you fetch a branch, you're done for this cycle with a fetch width of 3. Le 06/04/2016 18:

Re: [gem5-users] checking of sw-sw order violations

, Arthur Perais. Le 29/03/2016 15:41, Abhishek Rajgadia a écrit : In the checkViolations() function in lsq_unit_impl.hh , it is mentioned in a comment that it checks if load/store incorrectly passed a store. Does it really check if store incorrectly passed a store? Since it checks the LoadQueue

Re: [gem5-users] use of depCheckShift parameter in memory order violation check

ilman/listinfo/gem5-users -- Arthur Perais INRIA Bretagne Atlantique Bâtiment 12E, Bureau E303, Campus de Beaulieu 35042 Rennes, France ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] L1 cache configurations

hes, I got an error: /Segmentation fault (core dumped)/// Is it possible to configure gem5 as to run a system with a fully associative cache? ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-u

Re: [gem5-users] Cache line in gem5

man/listinfo/gem5-users -- Arthur Perais INRIA Bretagne Atlantique Bâtiment 12E, Bureau E303, Campus de Beaulieu 35042 Rennes, France ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] arm, aarch64: asymmetry between load-pair and store-pair implementation

econd one is if it sounds reasonable to do the one micro-op only solution (although for completeness, any 128-bit store currently cracked into two micro-ops should be reimplemented). Cheers, Arthur Perais. -- Arthur Perais INRIA Bretagne Atlantique Bâtiment 12E, Bureau E303, Campus de Beau

Re: [gem5-users] Error on gem5.debug but no error on gem5.fast

egards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Arthur Perais INRIA Bretagne Atlantique Bâtiment 12E, Bureau E303, Campus de Beaulieu 35042 Rennes, France ___ gem5-users mailing

Re: [gem5-users] Parsec in X86 FS mode uses not all cores in O3

ilman/listinfo/gem5-users -- Arthur Perais INRIA Bretagne Atlantique Bâtiment 12E, Bureau E303, Campus de Beaulieu 35042 Rennes, France ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] x86 Instruction missing serialize flag

eally find anything related on the mailing list). Best, -- Arthur Perais INRIA Bretagne Atlantique Bâtiment 12E, Bureau E303, Campus de Beaulieu 35042 Rennes, France ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] CPU Configuration

s a decode queue between Decode and Rename/Allocation and 2 instruction queues (because SMT) between the fetch buffer and the decode queue. Le 05/11/2015 13:31, Virendra Kumar Pathak a écrit : Hi Arthur Perais, Thanks for your response. I have a question regarding blocking & unblocking o

Re: [gem5-users] CPU Configuration

x27;t get higher than necessary restart penalties when the pipeline stalls because of resource contention (e.g., full ROB). 2) Instructions are added to the unified instruction queue at Dispatch (iew_impl.hh) and scheduled in scheduleReadyInsts() in inst_queue_impl.hh. Cheers, Arthur Perais.

Re: [gem5-users] checkpoint with O3 cpu

memdep predictor). Cheers, Arthur Perais. - Mail original - > De: "Jianghao Guo" > À: "gem5 users mailing list" > Envoyé: Samedi 24 Octobre 2015 15:35:30 > Objet: [gem5-users] checkpoint with O3 cpu > From my understanding, when we do checkpoint,

[gem5-users] O3 Memory dependency predictor

res to the same location visible to other processors in order, and it will also take care of forwarding/squashing when it is needed. Am I correct in assuming that this simply creates false dependencies, or are there cases where this is really required? Cheers, Art

Re: [gem5-users] ready registers for effAddr

for address computation and if they are ready(for both load and store instructions) ? On Tue, Sep 1, 2015 at 2:25 PM, Arthur Perais <mailto:arthur.per...@inria.fr>> wrote: Abhishek, You can scan the memory dependency predictor (mem_dep_unit.hh) for entries that 1) Rel

Re: [gem5-users] ready registers for effAddr

->readyToIssue(), that will be true if both source registers are ready and the the memory dependency is satisfied. Hope it helps, Arthur Perais. Le 01/09/2015 06:34, Abhishek Rajgadia a écrit : Dear All, I am new to gem5. I am trying to figure out if memory instructions in the instruct

Re: [gem5-users] calcEA() function crashes

gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Arthur Perais INRIA Bretagne Atlantique Bâtiment 12E, Bureau E303, Campus de Beaulieu 35042 Rennes, France ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] X86 Detailed CPU

han 7 cycles (someone correct me if I'm wrong). On Apr 27, 2015 9:01 AM, "kassan unda" <mailto:kassanu...@gmail.com>> wrote: And yes I am using detailed cpu. On Apr 27, 2015 6:10 AM, "Arthur Perais" mailto:arthur.per...@inria.fr>> wrote:

Re: [gem5-users] X86 Detailed CPU

Ralph Waldo Emerson ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Arthur Perais INRIA Bretagne Atlantique Bâtiment 12E, Bureau E303, Campus de Beaulieu 35042 Rennes, France ___ gem5-use

Re: [gem5-users] IQ entry free, why does it wait till the instruction is committed to free itself.

mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Arthur Perais INRIA Bretagne Atlantique Bâtiment 12E, Bureau E303, Campus de Beaulieu 35042 Rennes, France ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] IQ entry free, why does it wait till the instruction is committed to free itself.

n on this would be great. I very well could be missing something/reasoning (there is a lot of code (: ) Thanks for your time. Kindly, Sam ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Arthur Pera

Re: [gem5-users] Runahead execution in Alpha implementation

ckpointing architecture, i.e. is checkpointing used to save register file state to support runahead execution? Thanks. ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Arthur Perais INRIA Bretagne

Re: [gem5-users] Comparing application outputs in a loop

he other is always faulty because of random fault injections. I would like to know how such comparison is possible in gem5 and how I can do that. I would appreciate any help. Azadeh ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.or

Re: [gem5-users] Re-Executing LAS Conflicts

references on replay : Understanding Scheduling Replay Schemes by Kim and Lipasti Recovery mechanism for latency misprediction by Morancho et al. They deal with latency misprediction and not memory order violation, but they do discuss selective replay. Hope it helps. -- Arthur Perais INRIA Bretagne

Re: [gem5-users] Re-Executing LAS Conflicts

users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Arthur Perais INRIA Bretagne Atlantique Bâtiment 12E, Bureau E303, Campus de Beaulieu 35042 Rennes, France ___ gem5-users mailing list gem5-users@gem5.org

[gem5-users] [X86] Changing instruction type in ISA definition

). Am I looking in the wrong place here? Thanks in advance, -- Arthur Perais INRIA Bretagne Atlantique Bâtiment 12E, Bureau E303, Campus de Beaulieu 35042 Rennes, France ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Regarding CacheConfig.py and custom O3 models

ns.py it is set to 32kB. Can anyone check its config.ini files to confirm this (This could also be a mistake on my side :))? Thanks, -- Arthur Perais INRIA Bretagne Atlantique Bâtiment 12E, Bureau E303, Campus de Beaulieu 35042 Rennes, France ___

Re: [gem5-users] Writeback buffer kills O3 performance, what is it meant to model?

em5-users mailing list gem5-users@gem5.org <mailto:gem5-users@gem5.org> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Arthu

Re: [gem5-users] consistency issue with gem5

You can define new detailed models (following was was done for arm_detailed). For instance, one can use prefetcher A and the other one can use prefetcher B. You'll just have to modify some python files (Options.py amongst others) and create the ones defining the configuration of your new detaile

Re: [gem5-users] consistency issue with gem5

If you want to make sure that both execution are similar, you can use the util/tracediff script (http://www.m5sim.org/Debugging#tracediff). If they are, it simply means that prefetched blocks are considered as accessed blocks hence I guess it is normal to see different addresses between the two

Re: [gem5-users] consistency issue with gem5

Hi, I would guess that if your prefetchers predict different addresses then you will naturally access different blocks during the two runs. Does that make sense? Arthur. Le 24/07/2013 14:20, Mahmood Naderan a écrit : Hi I have a concern about gem5 simulator consistency and will be glad for a

Re: [gem5-users] O3 Timing

Le 17/07/2013 17:01, Jianghao a écrit : Thanks for your clarification. So even all resource like operands/FUs are available, the instruction still need to wait issueLat cycles before execution, correct? Well it's more like the FU does not become available until issueLat cycles. Is there a

Re: [gem5-users] O3 Timing

My understanding is that issueLat is the minimum number of cycles you have to wait before scheduling an instruction of the same type on the FU. Specifically, if opLat is 6 and issueLat is 1, you have a pipelined unit with a latency of 6 cycles but you have a throughput of 1 op/cycle once the pi

Re: [gem5-users] Execution time of Mul and load

The reason is that although the functional units latency are well defined, the instruction are all steered to the ALU unit because their type is wrong (inst->staticInst->_opClass is wrong). This is because the ISA definition lacks some information. Alternatively you can set it by hand depending

[gem5-users] Statistics issue

to match the number of threads specified in the python script by hand is not very elegant. Cheers, Arthur Perais. ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Max number of accesses to the branch predictor in a cycle

Isn't it rather "fetchWidth or until the first taken branch"? Le 25/04/2013 11:10, Fernando Endo a écrit : Hello, I'm using the stable gem5 (jun 2012). Taking a look at the DefaultFetch::fetch method (src/cpu/o3/fetch_impl.hh), I found that the branch predictor can be accessed more than once

Re: [gem5-users] About number of source regs

Hi, First of all, a little disclaimer : I am not absolutely sure that my explanations are correct since it has been a long time I updated my version. However, last time I checked, that is how I understood it. But first, do you have a particular example of a XOR or a AND with more than 2 sour

Re: [gem5-users] Is it possible to use L2 prefetch with AtomicCPU?

To my knowledge, you cannot use caches with the AtomicCPU, hence, you cannot use the Prefetcher. Le 13/02/2013 15:13, Mr. Orangeade a écrit : I've added StridePrefetcher to the L2Cache object but don't see any effect of prefetching. It looks like it simply doesn't work. At the same time it wor

Re: [gem5-users] Why are the detailed ARM CPU's memory hierarchy access times all crazy?

code you show is the execution latency of the load/store /execution/ in the functional unit, but it is in no way the latency of the memory. Similarly, you will probably see the ALU at one cycle and the IntMult at more than one cycle. Hope it helps. Arthur Perais. Le 09/02/2013 04:53, Gabriel

[gem5-users] [X86-O3] Instruction class not properly defined

configuration somewhere I guess) or from the ISA definition. PS : In the wiki, there is a definition of the microops used in the X86 implementation, but there is none (that I found) for SSE. Does it exist or do I have to go fish in the .isa files? Arthur Perais

[gem5-users] [O3] Early D-Cache access on store execution

still be written in-order...won't they? Thanks for reading, Arthur Perais. ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] O3 X86: Incorrect branch direction for jumps inside microcode

is not relevant to the issue I am seeing here. I hope it helps and let me know if you need any more information. Thank you, Arthur Perais. Le 28/09/2012 21:09, Andrea Pellegrini a écrit : Hi Arthur: interesting, I don't recall seeing this behavior in my experiments (it seems to happen

[gem5-users] O3 X86: Incorrect branch direction for jumps inside microcode

o change the PCState.branching() function so that it is able to deal with jumps inside a macroop. However, this also raises the following question: shouldn't we embed information about the current uop when we query the branch predictor? Best regards, Arthur Perais. ___