Hi again,
I'm not sure what you mean in 1. Maybe I minsunderstood what it is you
call forwarding.
2. Yes, the pipeline will behave like this. And if issueToExecute is 2,
is will behave like that:
Instr1 F D R I I E W C
Instr2 F D R - I I E W C
While it should ideally behave like that:
Instr1 F D R I I E W C
Instr2 F D R I I E W C
as Instr2 should catch the operand produced by Instr1 on the bypass network.
Arthur.
Le 26/11/2016 à 21:21, fami Hoseini a écrit :
Arthur,
Thank you so much for your reply. I still have some questions though.
1. Does your answer mean that if we set the parameter to 1, then we
have forwarding only from IEW stage to another IEW stage and not
between other stages? And this forwarding is only based on a register
to be ready or not, i.e., whenever an inputs of an instruction are
ready it can be executed.
2. Regarding the Issue to Execute latency. If the latency is set to
one then for two instructions 1 and 2 (2 is dependent to 1) the
pipeline should be something like this:
Instr1 F D R I E W C
Instr2 F D R I E W C
Please correct me if I'm wrong. Then when the result of instr1 becomes
available at its E stage, the I stage of instr2 can issued instr2 at
the same cycle?
Thank you,
Fateme
On Wed, Nov 23, 2016 at 12:23 PM, Arthur Perais
<[email protected] <mailto:[email protected]>> wrote:
Hello Fateme,
I hope I got your question right, so let me try to answer.
Short answer is gem5 o3 does not implement register forwarding.
Long answer is that it kind of does if you keep a parameter set to
one. If your issueToExecute latency is greater than one, then two
dependent instructions will never execute back-to-back,
so the processor behaves as if instructions always read operands
from the PRF and pay issueToExecute - 1 cycles to do it (although
I'm pretty sure writing to the PRF takes 0 cycle in the o3 model).
That being said, the base
configuration of gem5 behaves as if register forwarding is
implemented because the issueToExecute latency is 1 (and you
should leave it at that unless you implement forwarding and
speculative scheduling).
So, in a given cycle, assuming the issueToExecute latency is set to 1.
1 - Some instructions are executed and their result become available.
2 - Some instructions are woken-up using the newly available results.
3 - Some instructions are scheduled for execution in
issueToExecute cycles (so 1 in our example).
Thus, two dependent instructions are allowed to execute
back-to-back (even with loads). So really, it's more that reading
a register is free rather than having forwarding, but
performance-wise, it's relatively similar.
Arthur.
------------------------------------------------------------------------
*De: *"fami Hoseini" <[email protected]
<mailto:[email protected]>>
*À: *[email protected] <mailto:[email protected]>
*Envoyé: *Mercredi 23 Novembre 2016 17:30:42
*Objet: *[gem5-users] O3 CPU register forwarding
Hi,
I'm trying to make modifications to O3 CPU. I want to know if
this cpu implements register forwarding? If yes, how this
communication is implemented (It seems to me that timebuffer
is not used for that purpose)?
This question was asked before:
https://www.mail-archive.com/[email protected]/msg02327.html
<https://www.mail-archive.com/[email protected]/msg02327.html>
But no answers was provided for that. Maybe I'll have a better
luck to get the answer.
Thank you,
Fateme
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