Yes. The source repos used to make those kernels is the same as the source
repos referenced here:
http://gem5.org/ARM_Linux_Kernel
Cheers,
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Tue, Dec 2, 2014 at 1:02 PM, Guru Prasad wrote:
> Hi,
>
> Are the kernel sources also
These patches will give an idea, and they're not difficult to port.
http://repo.gem5.org/linux-patches/
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Thu, Nov 6, 2014 at 3:38 PM, Sanem Arslan via gem5-users <
gem5-users@gem5.org> wrote:
> Hello,
>
> I want to
tarball on the download page.
Work on a more up-to-date Android filesystem and kernel is still underway.
Thanks,
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
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Because of some of the recent changes to aarch64 in gem5, you need to use a
newer kernel and dtb file. Instructions for how to obtain them are here:
http://gem5.org/ARM_Linux_Kernel
I think we will be releasing tarballs with newer kernels/images soon.
Anthony Gutierrez
http
care about? I.e., should users just modify this manually if they
want to use gdb with 32 bit ARM, or would a patch that fixes this be
welcomed?
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Tue, Aug 19, 2014 at 1:15 PM, Anthony Gutierrez
wrote:
> I'm trying to use gdb to debug a
desc. I am using the latest source from the
gem5 dev repo. However, I am still experiencing the Remote 'g' packet is
too long: ... error. Has anybody experienced this recently? Seems as though
it was working a year ago.
Anthony Gutierrez
http://web.eecs
or use the real FP. I'd guess that softFP usually does a
better job of optimizing that forcing all FP instructions to be done in
hardware, and that hardFP is only used when you have code that needs to be
hand optimized.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Thu, Jul 31,
n the wiki:
ejre-7u60-fcs-b19-linux-arm-vfp-sflt-client_headless-07_may_2014.tar.gz
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Wed, Jul 30, 2014 at 4:57 PM, jerry yin wrote:
> Hi Anthony,
>
> Thanks for your reply. I think so. I just redo installing java on the img
>
gem5
terminal. You should be able to to install Java on the image without the
gem5 source at all.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Wed, Jul 30, 2014 at 2:51 PM, jerry yin wrote:
> Hi Anthony,
>
> I just built gem5 from scratch all over again. Same problem happ
You must not be setting up the image properly. Make sure you have qemu
installed, that you mount the image properly, and that you install
everything correctly. It's impossible to know what you're doing incorrectly
as I cannot reproduce the error.
Anthony Gutierrez
http://web.eecs
08.tgz
As it has some open-source libraries you need for Java already installed.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Tue, Jul 29, 2014 at 12:49 PM, jerry yin via gem5-users <
gem5-users@gem5.org> wrote:
> Hi all,
>
> I'm trying to install and run ja
For ARM you definitely can. Use the patch and kernel config contained here:
http://www.gem5.org/dist/current/arm/vmlinux-emm-pcie-3.3.tar.bz2
And the kernel source here:
http://www.gem5.org/dist/current/arm/linux-arm-arch.tar.bz2
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Tue
>
> Cordialement / Best Regards
>
> SENNI Sophiane
> Ph.D. candidate - Microelectronics
> LIRMM - www.lirmm.fr
>
> Le 18/07/2014 15:59, Anthony Gutierrez via gem5-users a écrit :
>
> We did some work on this at the University of Michigan. Here is the
> relevant publi
We did some work on this at the University of Michigan. Here is the
relevant publication.
http://web.eecs.umich.edu/~atgutier/papers/ispass_2014.pdf
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Fri, Jul 18, 2014 at 9:53 AM, senni sophiane via gem5-users <
gem5-users@gem5.org>
Working on it as we speak. Will be up in about 30 mins. Also reflects the
changes in review 2298.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Tue, Jun 24, 2014 at 12:58 PM, Ali Saidi wrote:
> Speaking of, could you address the two comments on the patch so we can
>
Sorry. Forgot the link.
http://reviews.gem5.org/r/2174/
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Tue, Jun 24, 2014 at 10:33 AM, Anthony Gutierrez
wrote:
> Hi,
>
> Here is an example patch that adds a new branch predictor; in particular
> it adds the bi-mode bran
Hi,
Here is an example patch that adds a new branch predictor; in particular it
adds the bi-mode branch predictor. It's pretty straight forward.
There are some problems with that patch though, which reminds me I need to
update it so it can be shipped.
Anthony Gutierrez
The latest version of the README has all the steps necessary to build the
kernel, image, and dtb files.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Wed, Apr 9, 2014 at 2:01 PM, Neal Haas wrote:
> Thanks for the fast response Anthony.
>
> I have followed these instruc
There is an updated readme in that tarball that contains detailed
instructions for how everything in the tarball was built.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Wed, Apr 9, 2014 at 1:40 PM, Neal Haas wrote:
> Hi all,
>
> I'm trying to understand how the v
data.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Sat, Mar 8, 2014 at 9:23 AM, senni sophiane wrote:
> Hi everybody,
>
> In stats file, I can find "dcache.WriteReq_accesses" corresponding to the
> number of write request accesses in D-Cache. However, there is no
Are you using the python scripts that are provided on that page?
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Tue, Feb 25, 2014 at 2:04 PM, Aditya Deshpande <
adityamdeshpa...@gmail.com> wrote:
> Hi,
>
> I am following the information provided in the gem5 we
Here would be good: http://gem5.org/BBench-gem5
Have you confirmed this patch works with the latest version of gem5? I
think some m5ops have been added/modified.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Tue, Feb 11, 2014 at 12:47 PM, Martin Brown wrote:
> Sure I can do t
What exactly are you setting to 32, 256, 1024, etc.? The local, global, or
choice predictor? Or all 3?
You can try getting a trace of the branches by using gem5.opt
--debug-flags=Fetch. That way you can see if the predictions are behaving
as expected.
Anthony Gutierrez
http://web.eecs.umich.edu
r
increases aliasing probability drops and he number of mispredictions ought
to drop (unless a corner case happens)
On Thursday, January 16, 2014, Anthony Gutierrez wrote:
> I'm not quite sure exactly what it is you're doing, but if I am following
> correctly it doesn't seem like
e behavior describing could be
reasonable.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Thu, Jan 16, 2014 at 9:01 PM, Milad Mohammadi wrote:
> Hi,
>
> The gem5 local branch predictor exhibits a larger number of mispredictions
> as you increase the size of the predictor.
I like to use the Linaro toolchain:
http://www.linaro.org/downloads/
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Wed, Jan 15, 2014 at 3:35 PM, Yu Wang wrote:
> Hi,
>
> I have some issues with the ARM cross compiling tools. Specifically,I am
> trying to install J
there actually be
something separate called Debug_Enable_Pri? If this is ok, I can submit
this patch.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
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scripts to switch to a detailed CPU and enter back into simulation.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Wed, Aug 28, 2013 at 9:36 AM, יואב אורן wrote:
> Hi,
>
> I'm running Parsec benchmark with 1 or 4 CPUs with the Disk image from
> http://www.cs.utexas.edu
That is the inverse of the BW, i.e., the time in picoseconds.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Thu, Aug 22, 2013 at 5:32 PM, Lu Bai wrote:
> Hi all,
>
> I'm trying to change the bandwidth of SimpleMemory, the default value is
> 12.8GB/s and the simula
but it was several years ago and I was
just trying to get some more apps to work on gem5.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Sun, Aug 11, 2013 at 6:14 PM, Xiangyang Guo wrote:
> Anthony,
>
> Thank you so much.
>
>
> On Sun, Aug 11, 2013 at 6:09 PM, Anthon
Here are the contents of the rcS for Replica Island I wrote:
#!/bin/sh
#Author: Anthony Gutierrez
sleep 10
/sbin/m5 dumpstats
/sbin/m5 resetstats
am start -n com.replica.replicaisland/.AndouKun
/sbin/m5 exit
I haven't tested it in a few years so I don't know if it still works, I&
sizes
should be made much smaller.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Mon, Jul 15, 2013 at 2:43 PM, Xiangyang Guo wrote:
> Hi, I make the InstQueue size to 1 to make sure inorder issue, but I did
> not make any change to ROB because I think ROB doesn't harm
value on
commit.
Maybe someone who knows gem5's implementation can correct me on this.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Mon, Jul 15, 2013 at 2:40 PM, Korey Sewell wrote:
> Hi Tony,
> Are you saying that registers are *not* being freed upon commit?
>
> E
you need to
set physical registers >= max number of arch registers + max number of
instructions in flight (ROB size).
Perhaps you're running into a similar issue with your rename changes.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Mon, Jul 15, 2013 at 1:56 PM, Xiangyang G
available anywhere?
Thanks
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
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s = floorLog2(size) - 17; will yield a negative number.
Then, it tries to allocate a huge amount of memory, i.e., new FALRUBlk
*[numCaches];
See the ctor in fa_lru.cc
To override FA LRU tags see:
http://qa.gem5.org/42/how-to-set-a-fully-associative-l1-cache
Anthony Gutierrez
http://web.e
gem5 implements pseudo-ops. See src/sim/pseudo_inst.hh/cc
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Tue, May 14, 2013 at 7:57 PM, Mahshid Sedghi wrote:
> Hello,
>
> I was wondering if gem5 implements magic instructions. I need to
> distinguish between the two
I recommend using the latest development repository. The CPUs are
switching, but if you want to switch between atomic and O3 CPUs you need to
modify the CPU type of the repeat switch CPUs in Simulation.py.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Mon, May 13, 2013 at 10:51 PM
That is a little tricky. An easy way to do this is to retain them on the
image by disabling the CoW layer. Although you need to be careful with this
and probably use separate images for each file you need generated.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Mon, Apr 15, 2013 at
a/src/mem/cache/builder.cc
+++ b/src/mem/cache/builder.cc
@@ -88,11 +88,7 @@
{
int numSets = size / (assoc * block_size);
-if (numSets == 1) {
-BUILD_FALRU_CACHE;
-} else {
-BUILD_LRU_CACHE;
-}
+BUILD_LRU_CACHE;
return NULL;
}
Anthony Gutierrez
http://web
It is possible with the classic memory system. I don't know much about Ruby
but, from that assert it appears as though it's not possible in Ruby.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Tue, Mar 12, 2013 at 10:04 AM, Maxime Chéramy
wrote:
> Hello,
>
> When
while, but, I
finally got around to creating the wiki page. In it, I describe my
methodology for managing change in my local repo, i.e., by using mercurial
queues. I believe most of the gem5 devs make heavy use of MQs as well.
http://gem5.org/Managing_Change_in_Your_Local_Repository
Anthony Gutierrez
If you have the cds then you have the source and can build them yourself.
The binaries may not be distributed.
On Mar 8, 2013 4:52 PM, "Xiaobin Liu" wrote:
> Hi,
>
> Sorry to bother you guys, but could anyone kindly offer me a spec2000
> alpha binaries? The download link in SS website is 404 now.
Bytes.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Mon, Mar 4, 2013 at 3:03 PM, Ding, Hongyuan wrote:
> Hi all,
> I use the option of --cacheline_size=64 to define cache block size
> for dcache. But I wonder 64 means 64bits or 64bytes.
> Can an
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Sat, Mar 2, 2013 at 10:38 PM, Hossein Nikoonia wrote:
> I did this in Lion without a problem. Maybe you have multiple versions of
> gcc and that is confusing ...
>
>
> On Sat,
't working.
I'll have to start fresh and double check everything.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Sat, Mar 2, 2013 at 1:57 PM, Andreas Hansson wrote:
> Hi Tony,
>
> I use Xcode 4.6, and clang/clang++ as the default compiler (clang
> 3.2svn).
>
&
I tried clang, it also has linker errors. I'll try to figure out why the
llvm compiler that comes with my Xcode isn't working.
Thanks,
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Sat, Mar 2, 2013 at 10:50 AM, Ali Saidi wrote:
> HI Tony,
>
> I'm running 1
s@gem5.org/msg06632.html if I simply
run ./build/ARM/m5.fast configs/example/fs.py. Any help would be
appreciated.
Thanks,
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
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e sky for me...but it hasn't so far! :)
>
> -Korey
>
> On Tue, Feb 26, 2013 at 6:38 AM, Ali Saidi wrote:
>
>> **
>>
>> If memory serves the change breaks the o3 cpu for Alpha.
>>
>>
>>
>> Ali
>>
>>
>>
>> On 26.02.20
Can we push that patch out?
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Tue, Feb 26, 2013 at 8:39 AM, WonSeob Jeong wrote:
> Hi, Korey
>
> Thank you for your help!
> I applied hwrei patch and it works fine.
>
> Won Seob Jeong
>
>
> On 02/26/2013 0
likely to see it being used. If you run BBench, it will be used heavily.
Unless you're doing research in this specific area I wouldn't worry about
that instruction not being implemented.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Tue, Feb 26, 2013 at 3:48 AM, Abu Saad wro
I would never advocate such things... :-P
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Wed, Feb 20, 2013 at 5:33 AM, Jack Harvard wrote:
> Why not has a try "Download AndEBench apk" into Google?
>
> Jack Harvard
>
>
> On Tue, Feb 19, 2013 at 6:16
PK is
not distributed independently by the authors, I don't know how to get
access to the APK.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Tue, Feb 19, 2013 at 1:07 PM, Fangfei Liu wrote:
> Hi Anthony,
>
> ** **
>
> Thank you so much for your help! Do you kn
image.
Simply mount the image, then copy the apk file to /system/app. If you
notice there are a few APKs that I added to the Gingerbread image,
ReplicaIsland.apk and smartbench.apk. Both worked ok with this method.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Tue, Feb 19, 2013 at 11:16
lso I assume the regular detailed mode is also fairly similar to modern
> OoO CPUs?
>
>
> On Thu, Feb 14, 2013 at 10:59 PM, Anthony Gutierrez wrote:
>
>> The ARM detailed CPU is just the detailed CPU with certain parameters set
>> to model a modern OoO ARM CPU.
>>
&g
n advance!
>
>
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
> --
> Anthony Gutierrez <http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users>
> <http://m5sim.org/cgi-bin/mailman/
Hi Hongyuan,
switchcpu causes simulation to exit with the cause "switchcpu", it doesn't
actually cause a CPU switch. You could do something like this: add
"/sbin/m5 switchcpu" to your rcS script before you launch your benchmark.
Then you will need to modify the Simulation.py script to recognize th
Hi Gabriel,
I have finished a new version of BBench, version 3.0, you can get it here:
http://bbench.eecs.umich.edu
That site is still under heavy construction and I haven't officially
announced the release yet, so there isn't a ton of info; the new version is
written in html5 and is able to inte
I get an assertion failure when I repeatedly switch with the O3 CPU:
m5.opt: build/ARM/cpu/o3/fetch_impl.hh:432: void
DefaultFetch::drainSanityCheck() const [with Impl = O3CPUImpl]:
Assertion `!memReq[i]' failed.
Program aborted at cycle 10476827000
I am trying to run bbench on gingerbread with
Right. But, as was also pointed out, this makes it a completely different
benchmark. Just a word of caution.
-Tony
On Wed, Jan 23, 2013 at 2:59 PM, Jack Harvard wrote:
> As somebody on the list said, you can isolate the 11 pages into 11
> parallel runs on your cluster. You need to configure the
I am confused as to what you want to do. Do you want to run only one
webpage per run of the simulator? Or run separate instances of the browser,
each running a different page, in parallel?
In any case, if you want to eliminate any particular page from the
benchmark you need to mount the disk image
Did you look at logcat to see if it gives any hints as to what the problem
may be?
-Tony
On Mon, Jan 21, 2013 at 7:33 AM, huangyongbing wrote:
> Hi all,
>
> ** **
>
> I run bbench on arm platform using ics image downloaded from
> gem5’s website, and find that bbench stays at the fin
Are all of your runs on the same machine and/or with the same setup? Please
provide your exact command line and system setup.
-Tony
Hi Andreas,
** **
Thank you so much for your reply. I think my hg id is 94383c5124d2+ tip.
And sadly, I don’t think it happen at the exact same tips every time
Here is a patch for the 2.6.38.8 kernel that adds the necessary process
information:
diff --git a/arch/arm/kernel/m5op.S b/arch/arm/kernel/m5op.S
new file mode 100644
index 000..af56bc6
--- /dev/null
+++ b/arch/arm/kernel/m5op.S
@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2010 ARM Limited
+ * All
Hello Martin,
I am out of town at the moment. I will make my patches for the ARM kernel
available some time within a week.
-Tony
On Dec 5, 2012 10:21 AM, "Martin Brown" wrote:
> Hello Anthony,
>
> I'm a gem5 user. I'm running Android simulations. I'm trying to use the
> ProcessInfo methods, but
Can you provide some more information? What is your command line? Does the
simulation stop or fault? Does BBench ever start, what does the frame
buffer show?
That may be a warning that can be ignored.
-Tony
On Wed, Nov 7, 2012 at 2:42 AM, Aparna Mandke wrote:
> Hi,
> I am using ICS image and An
Yes. And I hope to add a draining regression soon.
On Nov 7, 2012 3:29 AM, "Andreas Hansson" wrote:
> Hi Tony,
>
> Could you give this one a go: http://reviews.gem5.org/r/1535/
>
> It seems to solve the problem on my end.
>
> Andreas
>
> From: Anthon
The default only has a shared L2 cache. If you wanted to use private L2
caches per core you'd need to instantiate num_cores L2 caches and L2
busses, then connect them to the CPUs. E.g., you have to do something like
this:
system.ls = [ L2Cache(clock = options.clock, size=...) for i in
xrange(num_c
There is a simple pipeline view in the util directory, this can be used for
debugging. Other than that, I don't know of any GUI for gem5.
-Tony
On Tue, Nov 6, 2012 at 5:33 PM, Payne, Benjamin wrote:
> Hello,
>
> I was playing around with AMD's SimNow, which has a GUI. Here are some
> examples:
NOTE, the problem with this trace is that it hangs while trying to drain
because the physmem never signals drained; it's dramWriteQueue is never
emptied and only refreshes forever.
-Tony
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Hi Andreas,
Actually, it appears the simple_dram does not drain properly at all in some
cases. You should be able to reproduce this error using a clean checkout (I
did add DPRINTFs to simple_dram.cc:drain()) without any modifications; the
following command line is what I ran:
./build/ALPHA/m5.opt
I have a system that repeatedly switching back and forth between core
types; I am trying to evaluate the effects on the caches due to switching.
I give each core its own L1 caches and when switching out, it keeps its L1s
connected. However, when I upgraded to the latest repo that uses simple
DRAM.
Hello,
I am running into an assertion failure, assert(!downstreamPending), in
MSHR::clearDownstreamPending(). This assert fails some of the time, but not
always. My question is, what is the difference between markedPending and
downstreamPending? It seems that marked pending is only every used insi
Those options are being ignored because you're not using caches at all. You
need --caches.
-Tony
On Thu, Nov 1, 2012 at 3:36 PM, Payne, Benjamin wrote:
> Hello,
>
> I am running gem5 in syscall emulation mode and specifying the cache
> sizes. This appears to work as desired.
>
> bpayne@bpayne-V
Hello,
I am trying to implement implement ownership forwarding on a snooped line
when a certain condition is met. I see in satisfyCpuSideRequest() that
ownership is forwarded by simply not asserting shared. Can the same be done
if I do not assert shared inside of handleSnoop()? Are they are any
co
The regular detailed config is modeled after a very aggressive OoO core, 8
way, with very large predictors and caches. One thing to double check is
that you are using the proper cache options (line size, size, assoc)
because these are overridden by the defaults if you just specify
--cpu-type=arm_de
For the stats you're not interested in, I think you can remove them from
the regStats() function of whichever object they belong to.
-Tony
On Wed, Oct 24, 2012 at 4:40 PM, Runjie Zhang wrote:
> Hello,
>
> I am trying to dump stats at very fine granularity so the size of the
> stats output fil
It doesn't necessarily depend on Ubuntu; it depends on having all the
libraries that Java depends on installed. It's easier to do with Ubuntu
(you can just apt-get all the packages). However, if you have an x86 image
with a suitable version of Linux you should be able to manually install all
depend
mptied.
>
> Steve
>
> On Tue, Oct 16, 2012 at 9:41 AM, Anthony Gutierrez wrote:
>
>> Hello Everyone,
>>
>> I am trying to clean and/or invalidate all cache lines during a drain. I
>> think I would need to iterate through every cache block and call
>> writeba
Hello Everyone,
I am trying to clean and/or invalidate all cache lines during a drain. I
think I would need to iterate through every cache block and call
writebackBlock() to put them in the writeback buffer. Anybody have any
suggestions on how to do this? I.e., how to prevent drain from completing
It seems as though it's running fine.
On Oct 13, 2012 6:02 AM, "Amit Singh" wrote:
> Hey...
>I have successfully built ARM architecture now I am trying to run
> gingerbread with bbench benchmark but it is taking so much of time as like
> it has stuck or stalled somewhre Below are the
ated syntax for specifying property
> 'sys.usb.config', use ${name} instead
> <3>init: using deprecated syntax for specifying property 'sys.usb.config',
> use ${name} instead
> [2.279438] init: using deprecated syntax for specifying property
> 'sys.usb.c
screen. I have a Core2Duo processor with 2 GB RAM. Can it
> be a problem of lack of main memory? I am waiting for about half an hour to
> 1 hour before terminating the process.
>
> On Sat, Oct 13, 2012 at 1:55 AM, Anthony Gutierrez wrote:
>
>> Please send all queries to the mailing lis
M. Can it
> be a problem of lack of main memory?
>
> On Sat, Oct 13, 2012 at 1:22 AM, Anthony Gutierrez wrote:
>
>> What is the error?
>> On Oct 13, 2012 1:18 AM, "Vedang Patel" wrote:
>>
>>> Hi,
>>> I am new to gem5. I am trying to run b
What is the error?
On Oct 13, 2012 1:18 AM, "Vedang Patel" wrote:
> Hi,
> I am new to gem5. I am trying to run bbench on Android ICS. But, I am
> not able to go past the boot screen. i am executing the following command
> in my terminal.
>
> /home/vedang/mercurial/gem5/build/ARM/m5.fast configs
m type*
> Can you let me know the file system that I have to refer?
> Thank you for your kindness again.
>
> Joosung Lee
>
> 2012/10/11 Anthony Gutierrez
>
>> It is possible to install some apk files by simply placing them in the
>> system folder. To do this you
It is possible to install some apk files by simply placing them in the
system folder. To do this you will need to mount the disk image on your
host machine and copy the apk over.
On Oct 11, 2012 1:13 AM, "이주성" wrote:
> Hello, I’m newbie to using the gem5.
>
> Sorry for that I’m such a beginner.
>
A number of users have observed errors with the VNC code. You can try
disabling the VNC stuff in gem5 or you can try to debug that error and find
out why it's happening.
-Tony
On Oct 9, 2012 7:25 AM, "Amit Singh" wrote:
> hi...
> I am trying to run bbench on gem5 simulating ARM. But following e
Try looking at the Caches.py and CacheConfig.py files.
-Tony
On Fri, Oct 5, 2012 at 9:27 AM, Pavlos Maniotis wrote:
> Can somebody help me find where to set cache memory parameters?
> For the time I care about Hit & Miss latencies etc...
> I use ALPHA ISA in fs mode and I run the splash2 benchma
behalf of Fangfei Liu [fangf...@princeton.edu]
> *Sent:* Monday, October 01, 2012 2:56 PM
> *To:* gem5 users mailing list
> *Subject:* Re: [gem5-users] questions on running benchmark on gem5
>
> Actually no. But I think the directory where checkpoint is located is
> shared by
If you look at configs/common/Simulation.py you can see what each options
does.
-Tony
On Mon, Oct 1, 2012 at 8:23 PM, Mahshid Sedghi wrote:
> Thanks for the quick response. What about standard switch (-s)? This is
> not also working?
>
>
> Mahshid
>
>
>
> On Mon, Oct
The "switchcpu" pseudo op only calls m5 exit, i.e., it's not fully
implemented. You could add a call to m5 exit to your rcS script right
before it launches your benchmark, then have the config script do a drain
and switch out the cpus.
-Tony
On Mon, Oct 1, 2012 at 7:47 PM, Mahshid Sedghi wrote:
30285 in raise () from /lib64/libc.so.6
>
> It seems that it failed at the assertion. Do you have any idea what's
> wrong with it? Thanks!
>
> Best regards
> Fangfei
>
>
>
> --
> *From:* gem5-users-boun...@gem5.org [gem5-users-b
I've used private L2 caches with the classic memory model. You should only
need to modify the CacheConfig.py file to create separate L2's and busses,
then connect them to their respective cores and to the membus.
-Tony
On Sun, Sep 30, 2012 at 3:41 PM, wrote:
> Hi All,
>
> I want to configure a
gem5.opt --outdir=bbench configs/example/fs.py -b bbench-gb
> --kernel=vmlinux.smp.mouse.arm --frame-capture --checkpoint-dir=bbench
>
>
>
>
> --
> *From:* gem5-users-boun...@gem5.org [gem5-users-boun...@gem5.org] on
> behalf of Anthony Gutier
ards
> Fangfei
>
>
> ----------
> *From:* gem5-users-boun...@gem5.org [gem5-users-boun...@gem5.org] on
> behalf of Anthony Gutierrez [atgut...@umich.edu]
> *Sent:* Sunday, September 30, 2012 12:59 PM
>
> *To:* gem5 users mailing list
> *Subject:
84GhCA0ZlhUlBjlhcqAIq2Ta4iw.&URL=http%3a%2f%2fwww.google.com%2fm%3fhl%3dmd%26gl%3dus%26source%3dandroid-browser-type%26q%3dewbay>.
> It is actually doing google search for ebay. Please find attached a
> snapshot for this page.
>
>
>
> Best regards
>
> Fangfei
>
>
/how you're running the simulation if you'd like help with this
problem.
-Tony
On Fri, Sep 28, 2012 at 11:31 AM, Anthony Gutierrez wrote:
> I've never seen this problem before, and the BBench source for eBay does
> not show anything called ewbay in the source, so I don'
I've never seen this problem before, and the BBench source for eBay does
not show anything called ewbay in the source, so I don't know how it's
getting redirected to that URL. Did you modify the BBench source in any
way? Can you send me your exact command line? And, can you tell me the
exact URL th
e that code as well as my
binary's code. Right now I can only see kernel code.
Thanks,
Tony
On Wed, Sep 19, 2012 at 3:17 PM, Ali Saidi wrote:
> **
>
> On 19.09.2012 14:30, Anthony Gutierrez wrote:
>
> I am trying to add debug symbol information for the benchmark I am
&g
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