Hello Jason,
Thanks a lot for your reply! I'm indeed aware that by the cache subsystem doing
this, it will give CPU the view of the load as happening before the store.
However, in view of the CPU commit order (the instruction order seen by the
CPU), the store must have committed before the load,
Thank you, Eliot.
I think this would give me what I need.
Priyanka.
On Wed, Mar 22, 2023, 11:55 AM Eliot Moss wrote:
> On 3/22/2023 12:09 PM, Priyanka Ankolekar via gem5-users wrote:
> >
> > Regarding the other part of your email:
> > Let me begin by saying I am a novice to both RISCV and gem5.
On 3/22/2023 12:09 PM, Priyanka Ankolekar via gem5-users wrote:
Regarding the other part of your email:
Let me begin by saying I am a novice to both RISCV and gem5.
I have a RISCV RTL with a certain config. I have set up gem5 to match that configuration. I want to
make sure that they are indeed
Regarding the other part of your email:
Let me begin by saying I am a novice to both RISCV and gem5.
I have a RISCV RTL with a certain config. I have set up gem5 to match that
configuration. I want to make sure that they are indeed equivalent so that
I can run some experiments on gem5 (instead of o
On 3/22/2023 11:11 AM, Priyanka Ankolekar wrote:
Sorry, I should have clarified. I am using the RISCV ISA in gem5.
(As you could have done,) I checked the gem5 sources,
and it *does* model that register, returning totalInsts
as gem5 calculates that. Presumably that is the same as
statistics wi
Hello,
This is a great question!
The short answer is I believe that the coherence protocol is correct.
(Though, there could always be unexpected bugs.)
The slightly longer answer: You are probably seeing that the store happens
before the load in "real" time. However, in the processors' view (i.e
Sorry, I should have clarified. I am using the RISCV ISA in gem5.
On Wed, Mar 22, 2023, 5:44 AM Eliot Moss wrote:
> On 3/22/2023 8:37 AM, Priyanka Ankolekar via gem5-users wrote:
> > Thank you, Eliot.
> >
> > Is there a way to probe minstret CSR to get the retired instructions?
>
> ?? What ISA
On 3/22/2023 8:37 AM, Priyanka Ankolekar via gem5-users wrote:
Thank you, Eliot.
Is there a way to probe minstret CSR to get the retired instructions?
?? What ISA are you talking about?
I doubt that gem5 would model such details of a processor
architecture. Maybe you should back up a little
Thank you, Eliot.
Is there a way to probe minstret CSR to get the retired instructions?
Thanks
Priyanka.
On Mon, Mar 20, 2023, 2:45 PM Eliot Moss wrote:
> On 3/20/2023 5:05 PM, Priyanka Ankolekar via gem5-users wrote:
> > Hi Eliot,
> > (Picking this up again after a while.) :-)
> >
> > Thank y
