[gem5-users] warn: DRAM device capacity (1024 Mbytes) does not match the address range assigned (256 Mbytes)

Dear all, who knows how to solve this warn when running programs? Btw, it seems not to make any effect on the correctness of programs. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_

[gem5-users] Re: A problem about using pseudo instruction in my own program

Hi,I follow your advice and have solved the problem successfully. Thanks a lot for your help. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)

[gem5-users] Re: A problem about using pseudo instruction in my own program

Hi, I see two problems with your implementation. First, where you call PIM in pseudo_inst.cc, you don't actually do anything with the result so it's just dropped. Second, in two_byte_opcodes.isa, you don't do anything with the result of PseudoInst::PIM. You need to put the result in RAX for it to b

[gem5-users] Re: multiple results in same state.txt file ?

What is the script you are running?  For example if you used dumpreset command, it will dump the stats until that point and then again at the end of the execution (for the stats gathered after the dumpreset command). On 4/29/20 11:34 PM, Furat Al-Obaidy via gem5-users wrote: please i have an i

[gem5-users] multiple results in same state.txt file ?

please i have an inquiry : why one the state.txt file contains multiple 3 or 4 times with different results : *Begin Simulation Statistics .. **End Simulation Statistics* how can control on the number of these , for example if we need just one result in state.txt file ? best regards Furat ./b

[gem5-users] Re: [UPDATE] gem5 Workshop with ISCA 2020

One last reminder... The deadline for abstracts for the gem5 workshop is on Friday. We're going to have both asynchronous contributions (e.g., videos and blog posts) and some synchronous time on something like zoom for authors and the community to interact. We'll have at least two synchronous time

[gem5-users] A problem about using pseudo instruction in my own program

I define a new pseudo instruction, but i can not get its correct return value in my program. The part of code is shown below. In include/gem5/m5ops.h: bool PIM(uint64_t in1, uint64_t in2, uint64_t out1, int kernel_id); In pseudo_inst.cc: case M5OP_RESERVED4: PIM(tc, args[0], args[1], args

[gem5-users] Re: How to access registers while processing cache miss?

Hi Jason, I'm asking can we read the registers (for example esp or cr3 etc..) while executing cache miss handler using packet object. Have a look at this post. In that one, he read the contents of esp. Is it the correct way to access