Hi all,
I changed to the kernel provided by UT Texas. And it can support at least 32
cores.
Thanks a lot.
Chao
On Aug 28, 2014, at 10:09 PM, Chao Zhang via gem5-users
wrote:
> Hi Andreas,
>
> I tried the alpha first. I found I have set up this ISA and I rebuild it for
> this test.
> It can
Hi,
As far as I know those are the only instructions that call suspend() on a
thread context in gem5 for the x86 ISA. This is all I found from grepping
the src/arch/x86 directories. But I'm not an expert on the x86 ISA, I just
touched this code because it was breaking regression tests.
The "459
You should be able to get a new working kernel with PCIe support for AArch64
like the following, however you’ll need all the patches that Andreas just
mentioned in an email to gem5-dev as committed next week.
wget
"http://www.linux-arm.org/git?p=linux-aarch64-gem5.git;a=snapshot;h=4003908898286
In that case whether the MSHR's would be shared between 2 L2 Caches or can
have separate MSHR for each L2 cache?
Thanks.
On Thu, Aug 28, 2014 at 11:52 AM, Andreas Hansson
wrote:
> Hi Prathap,
>
> Definitely. The gem5 memory system let’s you build any tree-topology you
> like, even unbalanced
Hi Prathap,
Definitely. The gem5 memory system let’s you build any tree-topology you like,
even unbalanced (L2 for one core, and no L2 for another etc, 2 core for one L2
and a single core for the next). Just instantiate an L2 per core, connect it
with a CoherentBus to the L1s of that core, and
Thanks Andreas. I have one more question regarding cache. Is it posible to
create a system with multiple L2 caches each private to a specific core?
On Wed, Aug 27, 2014 at 2:51 AM, Andreas Hansson
wrote:
> Hi Prathap,
>
> You can easily create a subclass of the BaseCache and give it suitable
Hi Andreas,
I tried the alpha first. I found I have set up this ISA and I rebuild it for
this test.
It can only support 4 timing simple alpha cores. And when I set the number of
cpu to 5, the m5 terminal output indicates CPU #4 (which is the 5th cpu) is
stuck.
So can I say it can only support
Hi Andreas,
I already flag "MicroHalt" as "IsQuiesce" in my last running. And I am not
using m5ops, so first part of your patch should not affect my running.
Therefore, as I mentioned in my last email, the waiting for
apic_timer_interrupt behavior still happens for certain instructions.
1) Is
Hi Hussain,
Write should work just fine. Are you sure there are actually any writes coming
from the L2?
Andreas
From: Hussain Asad via gem5-users
mailto:gem5-users@gem5.org>>
Reply-To: Hussain Asad
mailto:x7xcloudstr...@gmail.com>>, gem5 users mailing
list mailto:gem5-users@gem5.org>>
Date:
Hi Yan,
Check out: http://reviews.gem5.org/r/2369/
Perhaps the problem you are struggling with is even more complex, but at
least the patches on the review board should fix up a few issues.
Andreas
On 28/08/2014 03:27, "Zi Yan via gem5-users" wrote:
>Hi Mitch,
>
>After I applied two patches a
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