Re: [gem5-users] help : cc-NUMA in gem5

Hi Andreas, I just follow your instructions to build the NUMA config, but it does not work, gem5 would start to run and quit immediately, here is the debug ouput ===debug output begin=== command line: /vagrant/gem5/build/X86/gem5.opt gem5/configs/example/fs.py --num-cpus=4 --disk-image=x86

Re: [gem5-users] ARMv8 Client-Server configuration

Hi Ivan, The kernel that you’re using and the currently gem5 don’t support pci devices with arm64. I hope to remedy this within a week. Thanks, Ali On Aug 6, 2014, at 3:42 PM, Ivan Stalev via gem5-users wrote: > Hi everyone, > > I am trying to run a client-server setup using arm64. I am usi

Re: [gem5-users] An very easy problem about running MEVbench on X86

Hi Tang, Did you use the config file from: http://www.m5sim.org/dist/current/x86/config-x86.tar.bz2 I am able to compile a 3.2.60 kernel and run it. But when I tried 3.12.21, the kernel stuck at loading init process. -- Best Regards Yan Zi On 8 Aug 2014, at 18:13, Dongjie Tang via gem5-users w

Re: [gem5-users] An very easy problem about running MEVbench on X86

Tang, The kernel config file (which specifies how the kernel should be built right) lists all the devices and kernel parameters. There are too many to list, hence I said start with the config flag that the parsec x86 kernel uses (see the parsec gem5 from UT-Austin tech report). If your not sure if

Re: [gem5-users] An very easy problem about running MEVbench on X86

Hi Malek, Sorry to bother you again; how could you find which devices are not supported in gem5 as well as how do you disable them. Thank you very much for your help. Best Tang On Fri, Aug 8, 2014 at 5:58 PM, Malek Musleh wrote: > Hi Tang, > > This is likely happening because the custom kernel

[gem5-users] How to model on-chip DRAM?

Hello everybody, I'm trying to model on-chip DRAM that acts as the last level cache. The system I want to model has four WideIO controllers for the on-chip DRAM and two DDR3 controllers for the off-chip DRAM. I tried to add the on-chip memory controllers the same way I would add a shared L3 cache

Re: [gem5-users] An very easy problem about running MEVbench on X86

Hi Tang, This is likely happening because the custom kernel you built has flags for certain devices enabled, devices which are most likely not supported in gem5. I encountered this problem myself when building custom x86 kernels. I used the parsec x86 kernel flags as a starting point, and disabled

[gem5-users] An very easy problem about running MEVbench on X86

I made a kernel by myself, but when I run ' /mnt/nokrb/tangdj/gem5/build/X86/gem5.opt -d /mnt/nokrb/tangdj/gem5/Output/m5_augreal_1h configs/example/fs.py --script=/mnt/nokrb/tangdj/gem5/MEV/rcs_augreal/test_augreal_1h.rcS --cpu-type=detailed --caches --l2cache --kernel=/mnt/nokrb/tangdj/full-syste

[gem5-users] error when try resuming from checkpoint(gem5+dramsim2)

Hi everyone I am trying to use gem5 with dramsim2 and want to resume from the checkpoint I've created. But it always give me the error: m5.opt: build/ALPHA/mem/dramsim2.cc:291: void DRAMSim2::readComplete(unsigned int, uint64_t, uint64_t): Assertion `cycle == divCeil(curTick(), wrapper.clockPeriod

[gem5-users] difference between ROI and checkpoints

Hi, I'm wondering the difference between ROI and checkpoints. For checkpoints: the document mentions "checkpoints are dumped periodically". I understand that checkpoint is for later resuming the same workload. But why is periodic checkpoints necessary? From the m5out folder, it seems that taking

Re: [gem5-users] help : cc-NUMA in gem5

Hi Andreas, I just follow your instructions to build the NUMA config, but it does not work, gem5 would start to run and quit immediately, here is the debug ouput ===debug output begin=== command line: /vagrant/gem5/build/X86/gem5.opt gem5/configs/example/fs.py --num-cpus=4 --disk-image=x86