Re: [gem5-users] Doubt in SatisfyCpuSideRequest

2014-05-17 Thread Steve Reinhardt via gem5-users
If core 0's exclusive request reaches the L1-L2 bus before core 1's, then core 0 should suppress the cache response to core 1 and deliver the block directly via a cache-to-cache transfer after it receives (and writes to) its exclusive copy. The L2 would not end up with two MSHR targets, just the o

Re: [gem5-users] Building a 32-bit Linux disk image for hardfloat ABI compiled binaries

2014-05-17 Thread Ali Saidi via gem5-users
You can run cfdisk (or fdisk) on the image and see what it says. $ fdisk my.img Command (m for help): p Disk my.img: 536 MB, 536739840 bytes 16 heads, 63 sectors/track, 1040 cylinders, total 1048320 sectors Units = sectors of 1 * 512 = 512 bytes Sector size (logical/physical): 512 bytes / 512

Re: [gem5-users] Building a 32-bit Linux disk image for hardfloat ABI compiled binaries

2014-05-17 Thread Kiyeon Lee via gem5-users
Hi, Ali. Thanks for your quick response. How can I check and set the partition type to Linux (83)? Are there something else I need to do besides running the gem5img.py script? Thanks. --Kiyeon Seems like maybe the partition time isn't set to Linux (83)? Ali On 16.05.2014 10:37, Kiyeon Lee

[gem5-users] Doubt in SatisfyCpuSideRequest

2014-05-17 Thread biswabandan panda via gem5-users
Hi, If I have this scenario, 2 cores, 2 levels of cache L1(private), L2(shared) Both the cores have generated a miss for address X. Core 0 - a read exclusive miss (its a write request) Core 1 - a read miss Now L2 MSHR has two targets for address X. When the first target is popped out, in satisfyCp