Hi, If I have this scenario, 2 cores, 2 levels of cache L1(private), L2(shared) Both the cores have generated a miss for address X. Core 0 - a read exclusive miss (its a write request) Core 1 - a read miss Now L2 MSHR has two targets for address X. When the first target is popped out, in satisfyCpuSideRequest, the block is invalidated at L2 and the response sent to Core 0. For the second target the assert should have failed (in satisfyCpuSideRequest) assert(blk && blk->isValid()); But I have never come across this assert failing even for 64 cores running PARSEC benchamarks. How is gem5 handling this particular scenario? If the address X was dirty in L2, how is gem5 responding back? I am a bit confused. Any light on this will be of great help. Thank you for your time.
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