Re: [gem5-users] A readDisk error occurs when running gem5 in full system mode

Could you provide us with a gdb back trace of when this occurs? What version of gem5 are you using? Are you using a 32 bit or 64 bit host? There was a rather recent fix to (9533:dbf5a2fd479e) that fixed some issues when running on 32 bit platforms and having disk images > 4GB in size. Thanks,

Re: [gem5-users] Regarding shared L2 cache

It's not partitioned. Ali On May 27, 2013, at 2:28 AM, Ulkesh Deshmukh wrote: > Mahmood Naderan gmail.com> writes: > >> >> Yes >> Currenty I only set num_cpus to number of cores. I hope that this mean >> a shared L2 among all cores with one bank. So if the size is set to >> 2MB, then each co

[gem5-users] FW: [SPAM] Re: Mismatched stats between gem5 and performance counters when running BBench on ARM platform

Hi all, I have to recall the accuracy problem of gem5. When running BBench to gem5 platform, I want to know whether somebody have compared the microarchitectural metrics such as L1 instruction cache miss measured from gem5 and real hardware board. And which parameters should I change in

Re: [gem5-users] how .sm files communicate?

They follow a producer-consumer relationship. The slicc parser makes some module the consumer for this queue, and that module will call the dequeue for its producer. Take a look at build/X86/mem/protocol/L1CacheController.cc for instance, after you build your protocol. You will see lines like thi

[gem5-users] Deadlock occurred in creating and restoring checkpoints with fs_ruby in X86

Hi, I am using revision 9738+ and want to do FS mode simulation with ruby using O3CPU/Timing in X86 ISA. I am using hack_back script in configs/boot for fast booting of Linux. Here's the error I receive in both creating a checkpoint for fast boot as well as restoring it with timing CPU (the same h

[gem5-users] how .sm files communicate?

hi all Trying to understand Message Buffers & having a doubt: Consider message buffer from MESI protocol, L1 cache (requestFromL1Cache) > Definition: MessageBuffer requestFromL1Cache, network="To", virtual_network="0", ordered="false", vnet_type="request"; >Assignment: out_port(requestIntraCh

Re: [gem5-users] Restoring from checkpoint with Garnet aborts due to deadlock

Hi, I am using revision 9738+ and want to do FS mode simulation with ruby using O3CPU/Timing in X86 ISA. I am using hack_back script in configs/boot for fast booting of Linux. Here's the error I receive in both creating a checkpoint for fast boot as well as restoring it with timing CPU (the sa

[gem5-users] bug @ network tester (?)

function void NetworkTest::sendPkt(PacketPtr pkt) { if (!cachePort.sendTimingReq(pkt)) { retryPkt = pkt; // RubyPort will retry sending } numPacketsSent++; } should be buggy right? if retryPkt is non-null when this function is called, it is overwritten by the new value, and l

Re: [gem5-users] Address distribution CommMonitor

Thanks! The address mask is used smartly, but I am a bit reserved with its naming; I would select a name close to the purpose than the functionality; perhaps something like groupingMask (0: everything in one bin, max: each cell individually etc). For sure, will contribute back with scripts that ca

Re: [gem5-users] Multi-port DRAM controllers

Hi Amin, The short answer: put a bus in front of it. The gem5 CoherentBus is essentially a crossbar and to create a multi-port controller, the easiest way is to consider a xbar + multiple SimpleDRAM instances as a "unit". I hope that helps. Andreas From: Amin Farmahini mailto:amin...@gmail.c

Re: [gem5-users] Address distribution CommMonitor

You can play around with the address mask. By default it is 0xff….. (MaxAddr), but if you want to can make the LSBs 0 and thus "bin" the accesses or only look at certain ranges (could be interesting to see e.g. Bank distribution for a DRAM). Feel free to write up some Python scripts to

Re: [gem5-users] Make a new architecture/organization on gem5

Anybody Know how can I to create a new instruction ? Thank you in advance 2013/5/30 Andrws Vieira > Fernando, tomorrow I'll check your advices, so soon I'll have some result > I post here > > > []'s > > > 2013/5/30 Andrws Vieira > >> Hello, >> >> Merci Fernando ! >> >> If anybody have more s

[gem5-users] Multi-port DRAM controllers

Hi, My question is how to model a multi-port DRAM controller using SimpleDRAM? Let's say a DRAM controller is connected to two buses. In this case, the DRAM controller should have two ports, each connected to a bus. Thanks, Amin ___ gem5-users mailing l

Re: [gem5-users] Address distribution CommMonitor

Thanks Andreas! Is there a way to configure the bin size and/or # bins for reads and writes, like for other statistics? On Mon, Jun 3, 2013 at 11:53 AM, Andreas Hansson wrote: > Hi Mohammed, > > Don't change the class in src (or build). Rather change the > instantiation (in e.g. Fs.py or wh

Re: [gem5-users] Address distribution CommMonitor

Hi Mohammed, Don't change the class in src (or build). Rather change the instantiation (in e.g. Fs.py or where ever you added the monitors). When you instantiate it you can set the parameters, in this case disable_addr_dists to True : system.mem_monitor = CommMonitor(disable_addr_dists = True)

[gem5-users] Address distribution CommMonitor

Hi, I want to generate a heatmap of the addresses accessed in memory. I got a CommMonitor object hooked up but see two CommMonitor.py files, one under src/mem and another under build/. Which one should be modified? I suppose this needs no compilation afterwards, right? Is the heatmap dumped in sta

Re: [gem5-users] Mapping

the OS schedules the threads inside a cpu , isn't it ? , but there is certainly a code in the gem5 that divide an application into multiple threads and assign it to the cpus , no ? Can you please explain more ? I am very thankfull , Amina Hi Amina, > > If you run a full-system simulation it is

Re: [gem5-users] Timing CPU model

Hello All, I received clarification from qa.gem5.org( http://qa.gem5.org/132/timing-cpu-model) on this issue. "The TimingSimpleCPU is a 1 CPI CPU model that uses a timing back-end for memory latencies, so it's not surprising that you'd see little change in a cpu-bound benchmark when varying the c

[gem5-users] ticks vs clock cycles

Hi Everyone,Is tick just another number or it has some usefulness? What is its role?Why instead of clock cycles, ticks are printed as the events in most of the trace files?best,tod- 원본 메일 -보낸사람: "tod" 받는사람 : "gem5 users mailing list" 날짜: 2013년 5월 27일 월요일, 22시 26분 12초 +0900제목:

Re: [gem5-users] Mapping

Hi Amina, If you run a full-system simulation it is the guest OS that decides what thread executes where. Andreas From: amina belhaj messaoud mailto:amina.belhajmassa...@gmail.com>> Reply-To: gem5 users mailing list mailto:gem5-users@gem5.org>> Date: Monday, 3 June 2013 14:29 To: "gem5-users@

[gem5-users] Mapping

Hello , Is there anyone how can tell me where is the source code of the mapping in the gem5 simulator . I mean in which file it assigns workloads to the cpus in the full system mode ( for example when I execute a benchmark) thank you , Amina ___ gem5-

Re: [gem5-users] virtual_network : 0 / 1 / 2 meaning?

Thnx Nilay Trying to understand Message Buffers Just a doubt: Consider message buffer from MESI protocol, L1 cache (requestFromL1Cache) > Def: MessageBuffer requestFromL1Cache, network="To", virtual_network="0", ordered="false", vnet_type="request"; >Assignment: out_port(requestIntraChipL1Ne

Re: [gem5-users] Meaning of "warn: instruction 'fld' unimplemented"

Hi, Is it hard to implement them? I'm surprised there are not supported, how could it not be a problem for running a linux for instance? Thank you for your help, Maxime. 2013/5/24 Mahmood Naderan > Hi > That means specific floating point instructions are not implemented. > So they are ignored

Re: [gem5-users] Does gem5 provide the implementation of the full PCI communication protocol?

thanks! Maciej 2013/6/2 Ali Saidi > Hi Maciej, > > gem5 just provides enough of PCI config space so Linux can detect, > enumerate, and configure the device models. > > Ali > > On May 27, 2013, at 1:21 PM, Maciej Besta wrote: > > Hello everyone, > > I can see that gem5 somehow supports also PCI

Re: [gem5-users] Changing the Latency of SimpleMemory

Hi Amit, The easiest way would be to modify FSConfig.py where the memory controller it instantiated. You can simply add a latency = … and bandwidth = … based on the metrics you want. Andreas From: Amit Tara mailto:amit.t...@synopsys.com>> Reply-To: gem5 users mailing list mailto:gem5-users@ge

[gem5-users] Changing the Latency of SimpleMemory

Hi, I am running a bare metal application on ARM model in FS mode. I use the following command : build/ARM/gem5.opt configs/example/fs.py --cpu-type=arm_detailed --caches --bare-metal --kernel=sample_binary In the config.ini, I observed the memory is SimpleMemory with default latency of 3